Vendor: Altera Category: Channel Coding

Viterbi Intel® FPGA IP Core

The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implem…

Overview

The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implement a wide range of standard Viterbi decoders.Viterbi decoding (also known as maximum likelihood decoding or forward dynamic programming) is the most common way of decoding convolutional codes by using an asymptotically optimum decoding technique. In its basic form, Viterbi decoding is an efficient, recursive algorithm that performs an optimal exhaustive search. A convolutional encoder and Viterbi decoder are typically used together to provide error correction over a noisy channel. For example, a communications channel.

Key features

  • High-speed parallel architecture with
    • Performance of over 240 Mbps
    • Fully parallel operation
    • Enhanced block decoding and continuous decoding
  • Low-speed to medium-speed, hybrid architecture
    • Configurable number of add compare and select (ACS) units
    • Memory-based architecture
    • Wide range of performance and logic area
  • Fully parameterized Viterbi decoder, including:
    • Number of coded bits
    • Constraint length
    • Number of soft bits
    • Traceback length
    • Polynomial for each coded bit
    • Variable constraint length
  • Modulation support
    • Trellis coded modulation (TCM) option
  • Simulation and verification
    • VHDL testbenches to verify the decoder
    • Intellectual property (IP) functional simulation models for use in Intel FPGA-supported VHDL and Verilog HDL simulators
  • Interfaces and tools
    • Avalon® streaming interfaces
    • DSP Builder for Intel FPGAs

Specifications

Identity

Part Number
Viterbi Intel® FPGA IP Core
Vendor
Altera
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is Viterbi Intel® FPGA IP Core?

Viterbi Intel® FPGA IP Core is a Channel Coding IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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