Vendor: Altera Category: Channel Coding

5G Polar Intel® FPGA IP

The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with t…

Overview

The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration into your wireless design. Polar codes represent an emerging class of error correction supporting the high throughput requirements for 5G new radio (NR).

Key features

  • IP Functionality
    • Encode and decode supported
    • Run-time configurable code block length, code rate, frozen bit and parity check bit locations, optional re-configured for each code block
    • Code block length can be 32, 64, 128, 256, 512 or 1024
    • Optional built-in bit allocation with uplink Polar decoder or downlink Polar encoder
    • Optional CRC, including CRC6, 11, 16, 24a, 24b and 24c
    • Optional DCI format with RNTI scrambling for CRC24c
    • Optional interleaving/de-interleaving
    • Successive Cancellation List decoding scheme, compile-time configurable list size, choosing from 4 or 8
    • Decoder output buffering allows the downstream to receive result while the decoder processes the next data block
  • Performance specifications
    • Complies with the 3GPP 5G Polar specification
    • Performance figures detailed in the User Guide
  • User and system interfaces
    • Avalon®-Streaming (Avalon-ST) input and output interfaces
  • Debug and test capabilities
    • Provides C and MATLAB bit-accurate models for performance simulation and RTL test vector generation
    • Testbench and example design available

Block Diagram

Specifications

Identity

Part Number
5G Polar Intel® FPGA IP
Vendor
Altera
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is 5G Polar Intel® FPGA IP?

5G Polar Intel® FPGA IP is a Channel Coding IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP