USB2.0 HS/FS Controller

The Nuclei Universal Serial Bus (USB) Controller is compliant with the USB 2.0 Specification to support high-speed,full-speed or low-speed transfer when act as a host or peripheral.It’s a dual-role controller for On-The-Go (OTG) communications with another device, it support both Session Request Protocol (SRP) and Host Negotiation Protocol (HNP).The controller support up to
Transmit or Receive endpoints (including Endpoint 0). While endpoint 0 support Control transfer for enumeration process, the other endpoints support Bulk, Interrupt and Isochronous transfers. There is a FIFO in each endpoint to transmit or receive data, the FIFO address and depth could be configured. When act as a host, TX means OUT transaction and RX means IN transaction. When act as a peripheral, TX means IN transaction and RX means OUT transaction. For TX operation, CPU or DMA write data into FIFO, controller read from FIFO and send out. ForRXoperation, controller receive data and write into FIFO, CPU or DMA then read from it. Besides, the Internal DMA (IDMA) could access FIFO after configured. The controller could be configured to provides UTMI Low Pin Interface (ULPI) for high-speed transfer and FS PHY interface for full-speed and low-speed transfer, or a USB 2.0 Transceiver Macrocell Interface (UTMI) for all high-speed, full-speed and low-speed transfer.

• Compliant with the USB 2.0 Specification
• Supports dynamic host-peripheral switch of role
• Supports USB 2.0 host mode at high-speed (480 Mb/s), full-speed (12 Mb/s) or low-speed (1.5 Mb/s)
• Supports USB 2.0 peripheral mode at high-speed or full-speed
• Supports Control, Bulk, Interrupt and Isochronous transfers
• Supports high-bandwidth Isochronous and Interrupt transfers
• Supports Suspend and Resume signaling
• Supports remote wakeup in peripheral mode
• Supports HUB connection in high-speed host mode
• Up to Transmit and Receive endpoints (including Endpoint 0)
• Certified for high-speed OTG
• Supports SRP and HNP protocols
• Supports internal or external DMA access to Endpoint FIFOs
• Up to channels for the Internal DMA