ONFI 5.0 NAND Fash PHY IP Compliant to JEDEC
Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.
- Single-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
ONFI 5.0 NAND Fash PHY IP Compliant to JEDEC
Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.
Classical CAN, also known as CAN 2.0 Bus Controller IP, is the foundational CAN bus standard.
The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs.
The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol.
The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol.
The MIPI® D-PHY RX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
MIPI D-PHY/LVDS Combo Transmitter IP
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer…
HDCP 2 on HDMI / DisplayPort Embedded Security Module Firmware (generation 3)
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
1-port Receiver/Transmitter HDCP 2.3 on HDMI 2.0 or DisplayPort 1.4/2.0 ESM (generation 3)
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
The DisplayPort Link Policy Maker (LPM) is a DisplayPort 1.4/2.0 compliant software stack that manages and controls the DisplayPo…
The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.
The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB.
The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal…
The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
Gigabit Ethernet Media Access Control (MAC) SystemVerilog OVC VIP is fully documented,off-the-shelf component for the Developers …
USB 2.0 VMM System Verilog VIP
The USB 2.0 VMM SystemVerilog VIP is fully documented, off the shelf component for the verification of the USB 2.0 compliant Func…