MIPI SWI3S Manager Core IP

The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the Audio streams and the Control information together. One or more SWI3S Peripheral IP can be connected specific to the application.

The SWI3S Manager Controller Core can be configured specific to the physical interface (PHY) connected to the SWI3S sub-system

SWI3S Specifications Support

• Implements & supports MIPI SoundWire-I3S Specification

Control & Communication Features

• Supports sending timing information that enables multiple SWI3S Peripherals to send/receive data and generate audio sampling events
• Capable of commanding multiple SWI3S Peripherals using a control channel:
• Write to and read from Peripheral registers
• Collect Status and handle interrupts
• Supports management of Synchronization and Power State transitions (e.g., sleep/wake, clock, pause etc.)

Data Transport

• Supports management of shared data connection using half-duplex signaling with bit-level handover control
• Supports a row-based bitstream structure for bandwidth allocation
• Capable of scheduling link-wide synchronization points for audio and command streams

Audio and Clock Features

• Supports distribution of audio-quality clock to SWI3S Peripherals of multiple frequencies e.g., 19.2, 22.57, 242.0 & 24.57MHz
• Supports low latency transmission, ~300ns transport delay

Protocol & Physical Topologies

• Supports different Physical Layers (PHY) with features like impedance control & data encoding

Error handling and Calibration

• Error management for transport and protocol errors with appropriate recovery mechanisms & PHY calibration

• System Verilog RTL Source Code
• A simplified Testbench with simulation models to run initial set of tests after release
• Lint Report
• Synthesizable Netlist
• Synthesis Scripts and exception lists
• Timing Report
• Protocol Compliance & Coverage Report
• Sample Firmware with Drivers
• Application Notes