I3C protocol Controller

The Improved Inter Integrated Circuit (I3C) is part of a group of communication protocols defined by the MIPI Alliance. This specification is developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors.

The MIPI I3C Master Controller is a digital core that implements all protocol functions related to Main Master, Which as defined in the MIPI I3C Specification. The MIPI_I3C Core provides an interface between the system (application) and the I3C Interface, allowing the communication with the I3C devices and Legacy I2C devices (slaves) with limitations as specified in MIPI I3C Specification.

The Dual Role MIPI_I3C Controller can be configured as I3C Main Master or I2C Master/Slave with the processor interface (ICB). The controller meets the requirement of I3C protocol and I2C protocol as specified by the MIPI I3C Specification.

• Two Wire I3C serial interface - consists of a serial data line (SDA) and a serial clock (SCL)
  • Only support the role of Main Master, which sends the majority of the I3C Commands(CCC),
  • addressing either all Slaves(Broadcast CCCs) or specific individual Slaves(Directed CCCs)
• Only Single Data Rate messaging (SDR)
  • Broadcast message, which are sent to all I3C Slaves on the Bus
  • Direct message, which are addressed to specific Slaves
• Clock Stalling support in Master Mode
• Hardware assisted Dynamic Address Assignment (DAA)
• Detects arbitration loss due to incoming IBI and subsequently re-transmits the command
• In-Band Interrupt(without Payload) Processing
• Support DMA access for multi-buffer data communication
• FIFO size for RX and TX configurable at RTL level
• The Whole I3C Controller Design is Sync with one clock domain: ICB_CLK