Vendor: Packet Architects AB Category: Ethernet

Ethernet Switch VLAN 5x100M

Ethernet Switch VLAN 5x100M

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Key features

  • 5 x 100 Mbit/s Ethernet ports.
  •  Full wire-speed on all ports and all Ethernet frame sizes.
  •  Store and forward shared memory architecture.
  •  Support for jumbo packets up to 4087 bytes.
  •  Passes maximum overlap mesh test (RFC2899) excluding the CPU port, for all packet sizes up to 1518 bytes.
  •  Queue management operations:
    •  Disable scheduling of packets on a port.
    •  Disable queuing new packets to a port.
    •  Allow a port to be drained without sending out packets.
    •  Allow checking if a port is empty or not.
  •  Input and output mirroring.
  •  4,096 entry L2 MAC table, hash based 4-way.
  •  16 entry VLAN table.
  •  16 entry synthesized CAM to solve hash collisions.
  •  4 entries of the synthesized CAM are fully maskable.
  •  128 entry L2 multicast table.
  •  Automatic aging and wire-speed learning of L2 addresses. Does not require any CPU/software intervention.
  •  Spanning tree support, ingress and egress checks.
  •  L2 classification rules. Consists of Source Port, DA MAC, SA MAC, the packets VLAN VID field, the packets VLAN PCP field, the packets VLAN CFI field, Ethernet type.
  •  1310720 bits shared packet buffer memory for all ports divided into 2048 cells each of 80 bytes size
  •  4 priority queues per egress port.
  •  Configurable mapping of egress queue from IP TOS, MPLS exp/tc or VLAN PCP bits.
  •  Deficit Weighted Round Robin Scheduler.
  •  Egress queue resource limiter with four sets of configurations.
  •  Configuration interface for accessing configuration and status registers/tables.
  •  Multicast/Broadcast storm control with separate token buckets for flooding, broadcast and multicast packets.
  •  Multicast/Broadcast storm control is either packet or byte-based, configurable per egress port.
  •  LLDP frames can optionally be sent to the CPU.

Block Diagram

Ethernet Switch VLAN 5x100M block diagram

What’s Included?

  •  Unencrypted Verilog source code of IP.
  •  Datasheet of registers & theory of operations.
  •  C source code for accessing registers.
  •  Easy to parse YML file for register mapping.
  •  Verilog testbench.
  •  Low-level device driver.

Specifications

Identity

Part Number
Ethernet Switch VLAN 5x100M
Vendor
Packet Architects AB
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Packet Architects AB

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Frequently asked questions about Ethernet IP cores

What is Ethernet Switch VLAN 5x100M?

Ethernet Switch VLAN 5x100M is a Ethernet IP core from Packet Architects AB listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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