1-port Receiver/Transmitter HDCP 2.3 on HDMI 2.0 or DisplayPort 1.4/2.0 ESM (generation 3)
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
- Displayport
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
1-port Receiver/Transmitter HDCP 2.3 on HDMI 2.0 or DisplayPort 1.4/2.0 ESM (generation 3)
The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with and …
The DisplayPort Link Policy Maker (LPM) is a DisplayPort 1.4/2.0 compliant software stack that manages and controls the DisplayPo…
The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.
The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB.
The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal…
The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
Gigabit Ethernet Media Access Control (MAC) SystemVerilog OVC VIP is fully documented,off-the-shelf component for the Developers …
USB 2.0 VMM System Verilog VIP
The USB 2.0 VMM SystemVerilog VIP is fully documented, off the shelf component for the verification of the USB 2.0 compliant Func…
The 1394 OVC is a fully documented, off-the-shelf component using the Open Verification Methodology for quickly enabling function…
UART eVC is a fully documented, off the shelf component for Cadence Specman Elite functional verification environment.
USB OVA - USB 2.0 Function Controller OVA Checker IP
USB 2.0 Function Controller Checker OVA IP is fully documented, off the shelf component for the Developers of the USB 2.0 complia…
The USB 2.0 Vera RVM VIP is fully documented, off the shelf component for the Verification of the USB 2.0 compliant Function Cont…
The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect va…
The SafeSPI is a secure version of the SPI protocol that has been designed to provide enhanced security features, making it suita…
The SPI protocol specification supports high speed data transfer as per the peripheral specification, making it ideal for high - …
The I3c protocol, short for " Improved Inter - Integrated Circuit," is a communication protocol designed to improve upon the wide…
The I2C (Inter - Integrated Circuit) protocol is a widely used serial communication protocol for transferring data between electr…
DSP 10/100 100B-TX Ethernet PHY
SMS 10/100 ETHERNET PHY performs IEEE 802 10Base-T and 100Base-TX functionality as illustrated in Block diagram.
The Triple-Speed Ethernet FPGA IP core consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sub…
Intel® Stratix® 10 FPGA H-Tile FPGA production devices include a configurable, hardened protocol stack for Ethernet that is compa…