Protocol controller IP for a CAN FD light responder node
The FDLR_CAN is a CAN IP module that can be implemented in an ASIC, FPGA, and mixed-signal device.It supports CAN FD light respon…
- CAN / CAN-FD / CAN-XL
- now
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Protocol controller IP for a CAN FD light responder node
The FDLR_CAN is a CAN IP module that can be implemented in an ASIC, FPGA, and mixed-signal device.It supports CAN FD light respon…
Protocol controller IP for Classical CAN / CAN FD / CAN FD light commander and CAN XL
The XS_CAN is a low gate count CAN IP module that can be realized as stand-alone device, as part of an SoC, as part of an ASIC, o…
The Network on Chip (NOC) technology redefines typical NOC capabilities as it extends the on-chip network beyond chip(let) bounda…
USB Full Speed Transceiver
PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency ac…
UCIe Controller add-on CXL2 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller add-on CXL3 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
Controller + ATC + ATS + DTI · CXL.io · CXL.cache · CXL.mem · Memory pooling
Compliant with CXL Specification 2.0
Compliant to PCI Express base specification 5.0
Next-generation CMOS image sensor interface, SLVS-EC v3.0, is implemented in FPGAs SLVS-EC v3.0 Rx IP is an interface IP core tha…
A integrated hardware and software solution that includes a TSN-capable Ethernet switch, a DMA engine, an IEEE 802.1 AS Time Sync…
Size optimized, Silicon agnostic, Silicon Proven Ethernet PCS IP core for High Speed Ethernet applications The 200G/400G Ethernet…
10M/100M/1G/10G/25G Unmanaged Ethernet Switch
Silicon-Agnostic, Compact and flexible Ethernet Switch IPs Unmanaged Ethernet Switch IP cores are a family of Ethernet switching …
The DisplayPort 1.4 Transmitter PHY is for transmitting high-definition video and audio, making it an ideal choice for a wide ran…
Verification IP for CAN XL, FD and CAN 2.0
A comprehensive VIP solution portfolio for CAN XL, CAN FD and CAN 2.0 used by SoC and IP designers to ensure comprehensive verifi…
The IP is compliant to the new ISO 11898-1:2015 standard, supporting both standard CAN and CAN FD.
The MIPI I3CⓇ Total IP solution is a seamless integration of MIPI I3CⓇ controller, MIPI I3CⓇ PHY I/O, and MIPI I3CⓇ software stac…
The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.