Ethernet Switch/Router L2/L3/MPLS 12x10G

This L3 Ethernet Switch/Router IP core is built around a shared buffer memory architecture providing wire-speed switching and routing on all ports without head of line blocking. It offers dynamic allocation of packet buffers per port and priority to avoid starvation due to over-allocation. Advanced QoS features allow the most timing critical packets to get minimal delay while providing fairness between traffic classes.

No initial software setup is required and due to the hardware learning for MAC addresses the core is ready to receive and forward Ethernet frames immediately once powered up. There is a high performance processor interface for register configuration, and a high performance dedicated CPU port for slow path processing of packets.

The design is optimized for both FPGA and ASIC technology but does not have any dependencies on the underlying technology. If the target technology has TCAMs these can be utilized.

• 12 ports of 10 Gigabit Ethernet.
•  Full wire-speed on all ports and all Ethernet frame sizes.
•  Store and forward shared memory architecture.
•  Support for jumbo packets up to 16367 bytes.
•  Passes maximum overlap mesh test (RFC2899) excluding the CPU port, for all packet sizes up to 1601 bytes.
•  Queue management operations:
  •  Disable scheduling of packets on a port.
  •  Disable queuing new packets to a port.
  •  Allow a port to be drained without sending out packets.
  •  Allow checking if a port is empty or not.
•  Input and output mirroring.
•  4 source MAC address ranges with a number of different actions.
•  4 destination MAC address ranges with a number of different actions.
•  4,096 entry L2 MAC table, hash based 4-way.
•  4,096 entry VLAN table.
•  16 entry synthesized CAM to solve hash collisions.
•  4 entries of the synthesized CAM are fully maskable.
•  64 entry L2 multicast table.
•  Automatic aging and wire-speed learning of L2 addresses. Does not require any CPU/software intervention.
•  Spanning tree support, ingress and egress checks.
•  16 multiple spanning trees, ingress and egress checks.
•  VLAN priority tag can bypass VLAN processing and be popped on egress.
•  MPLS forwarding with support for swap,push,pop and penultimate pop operations.
•  4 entry VRF table.
•  1,024 * 4 hash based L3 routing table.
•  16 entry L3 routing TCAM.
•  1,024 entry next hop table. Pointed to from the routing entries.
•  1,024 entry packet modification table used by the next hop table to determine how build l2 fields in a packet to find the next hop.
•  Configurable ECMP support based on L3 protocol field,L3 Tos, and L4 SP/DP.
•  ECMP supports with up to 256 paths.
•  L2 classification rules. Consists of Source Port, DA MAC, SA MAC, the packets VLAN VID field, the packets VLAN PCP field, the packets VLAN CFI field, Ethernet type.
•  32 entry of classification / ACL consist of source port, routed flag, VRF IPv4 packet type, IPv6 packet type, MPLS packet type, source IP address, destination IP address, TOS, L4 type, L4 source port, L4 destination port, TCP flags.
•  Support for allowing L2 and L3 classification rules to be combined to larger than 5 tuple lookups.
•  5242880 bits shared packet buffer memory for all ports divided into 4096 cells each of 160 bytes size
•  8 priority queues per egress port.
•  Configurable mapping of egress queue from IP TOS, MPLS exp/tc or VLAN PCP bits.
•  16 ingress admission control entries.
•  Strict Priority Scheduler.
•  Egress queue resource limiter with four sets of configurations.
•  Configuration interface for accessing configuration and status registers/tables.
•  Multicast/Broadcast storm control with separate token buckets for flooding, broadcast and multicast packets.
•  Multicast/Broadcast storm control is either packet or byte-based, configurable per egress port.
•  LLDP frames can optionally be sent to the CPU