Vendor: Nuclei System Technology Category: GPIO

General Purpose Input/Output controller

The Nuclei LGPIO (Logic general-purpose I/Os) describes the operation of the Logic General Purpose Input/Output Controller(LGPIO).

Overview

The Nuclei LGPIO (Logic general-purpose I/Os) describes the operation of the Logic General Purpose Input/Output Controller(LGPIO). The LGPIO controller is a peripheral device mapped in the internal memory map. Each port bit of the General Purpose I/O(GPIO) Ports, can be individually configured by software in several modes(direction, pull up-enable, drive value and so on), as well as selecting between various sources of the controls for these signals(HW I/O Function).

Key features

  • Output states: push-pull or open-drain + pull-up/down
  • Output data from output data register (GPIOx_OVAL) or peripheral (alternate function output)
  • Input states: floating, pull-up/down
  • Input data to input data register (GPIOx_IVAL) or peripheral (alternate function input)
  • Bit operate agilely for each GPIO
    • Bit set (GPIOx_BIT_SET register)
    • Bit reset (GPIOx_BIT_RESET register)
    • Bit toggle (GPIOx_BIT_TOGGLE register)
  • Locking mechanism (GPIOx_MASK) provided to freeze the I/O port oval
  • Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions

Specifications

Identity

Part Number
GPIO
Vendor
Nuclei System Technology
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about GPIO IP cores

What is General Purpose Input/Output controller?

General Purpose Input/Output controller is a GPIO IP core from Nuclei System Technology listed on Semi IP Hub.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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