Overview
CMOS camera. It supports different data formats: YCbCr4:2:2/RGB565, BT656, BT1120, RAW and compressed data (JPEG).
It also ables to finish some simple image peocessing algorithm like data format transform, statistic histogram, image cropping and downsampling.
It has 9 output channels, which can output different data formates: RGB565, ARGB8888, image histogram, grey level, RAW, JPEG, R value, G value, and B value.
Learn more about MIPI IP core
With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.
Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.
High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.
From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.
The latest advancements in the MIPI D-PHY and MIPI C-PHY specifications and their potential to transform vision and imaging technologies.
Higher link speeds, security and a compliance program have been added to the MIPI Automotive SerDes Solutions framework.
