Vendor: Synopsys, Inc. Category: Soundwire

Verification IP for MIPI SoundWire

Achieves rapid verification closure of MIPI SoundWire devices operating with Basic and High-PHY links

Verification IP View all specifications

Overview

Verification IP for MIPI SoundWire achieves rapid verification closure of MIPI SoundWire devices operating with Basic and High-PHY links.

Key features

Specifications: SoundWire version v1.2​

DUT Types/Topology: Master, Slave​

Key VIP Features​

  • Serial Signal Interface, Multi-Lane support​
  • Passive Monitors​

Debug and Analysis​

  • Verdi based protocol and performance analysis​
  • Transaction log​, Verbosity Messages​, Debug ports​

Key Protocol Features​

  • Bank switching, Synchronization, Enumeration​
  • All types of resets, interrupts, test data, payload modes​
  • High-PHY, clock stop mode, dynamic number of slaves and clock frequency change​
  • All Frame Shapes and timing parameters​
  • Customization of Data Port parameters​
  • BRA, SDCA, Commit and Atomic access mechanism​

Test Suites / Groups Features ​

  • Includes AHB register interface​
  • Customizable FIFO interface & configurable numbers of Slaves​
  • Enables DUT register programming through customizable register interface​

Block Diagram

Specifications

Identity

Part Number
Verification IP for MIPI SoundWire
Vendor
Synopsys, Inc.
Type
Verification IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Synopsys' MIPI IP core

Frequently asked questions about SoundWire IP cores

What is Verification IP for MIPI SoundWire?

Verification IP for MIPI SoundWire is a Soundwire IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this Soundwire?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Soundwire IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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