Vendor: Baya Systems Category: Network-On-Chip

Configurable AMBA Non-Coherent Fabric IP

Flexible, High-Performance Connectivity for SoCs and Chiplet Systems Modern SoCs and chiplet-based systems require flexible, high-performance fabrics that can efficientl…

Overview

Flexible, High-Performance Connectivity for Advanced SoCs and Chiplet Systems

Modern SoCs and chiplet-based systems require flexible, high-performance fabrics that can efficiently connect a wide variety of non-coherent interfaces, memory, I/O, accelerators, and die-to-die links. As bandwidth, latency, and physical implementation requirements become more complex, fabric design must be optimized around real system KPIs rather than guesswork.

Baya’s Configurable AMBA Non-Coherent Fabric IP provides a flexible Network-on-Chip IP for high-performance SoCs and multi-chiplet designs, delivering high bandwidth, low latency, and built-in QoS and RAS. It natively connects AXI, APB, AXI-Lite, ACE-Lite, PCIe, HBM, DDR, and UCIe FDI interfaces through Baya’s scalable transport architecture.

Configured and optimized through FabricStudio, the fabric enables teams to explore topology, hierarchy, traffic patterns, and physical design constraints to meet bandwidth and latency targets while minimizing area and implementation risk. With support for advanced tiling, multicast, performance monitoring, and programmable QoS, it helps engineering teams build efficient, physically realizable non-coherent interconnects for scalable compute systems.

Key features

Native AMBA Non-Coherent Connectivity

Connect a wide range of AXI, APB, AXI-Lite, and ACE-Lite interfaces across CPUs, accelerators, PCIe controllers, memory controllers, coherent fabrics, and address-mapped peripherals.

High-Bandwidth Memory and I/O Integration

Enable efficient connectivity to PCIe, DDR, HBM, and UCIe-based die-to-die links with support for wide interfaces, multiple memory channels, and scalable high-throughput data movement.

Scalable Multi-Chiplet Architecture

Scale across up to 256 chiplets with flexible topology control, adaptive three-dimensional routing, and full topology customization through FabricStudio.

Performance Management and QoS

Use programmable bandwidth allocation, flow priority, route selection, input rate limiting, latency monitoring, and automatic QoS regulation to meet system-level performance goals.

Physically Aware, Deployment-Ready Design

Reduce implementation risk with advanced tiling, hierarchical design generation, RAS, debug, trace, performance monitoring, and PPA optimizations for scalable physical implementation.

Specifications

Identity

Part Number
Non-Coherent Fabric
Vendor
Baya Systems
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Network-On-Chip IP core

HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA

Network-on-Chip (NoC) architectures have become the standard interconnect fabric for many-core systems, yet most proposals face a fundamental trade-off between latency, area, and congestion management. This paper presents HyNoC (Hybrid Network-on-Chip), an open-source NoC architecture that combines circuit-switch path establishment with wormhole data transfer, targeting distributed computing systems built around VLIW processor cores on FPGA.

Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures

Ensuring Network-on-Chip (NoC) security is crucial to design trustworthy NoC-based System-on-Chip (SoC) architectures. While there are various threats that exploit on-chip communication vulnerabilities, eavesdropping attacks via malicious nodes are among the most common and stealthy. Although encryption can secure packets for confidentiality, it may introduce unacceptable overhead for resource-constrained SoCs.

Why verification matters in network-on-chip (NoC) design

In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Frequently asked questions about NoC IP cores

What is Configurable AMBA Non-Coherent Fabric IP?

Configurable AMBA Non-Coherent Fabric IP is a Network-On-Chip IP core from Baya Systems listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP