Configurable AMBA Non-Coherent Fabric IP
Flexible, High-Performance Connectivity for SoCs and Chiplet Systems Modern SoCs and chiplet-based systems require flexible, high-performance fabrics that can efficientl…
Overview
Flexible, High-Performance Connectivity for Advanced SoCs and Chiplet Systems
Modern SoCs and chiplet-based systems require flexible, high-performance fabrics that can efficiently connect a wide variety of non-coherent interfaces, memory, I/O, accelerators, and die-to-die links. As bandwidth, latency, and physical implementation requirements become more complex, fabric design must be optimized around real system KPIs rather than guesswork.
Baya’s Configurable AMBA Non-Coherent Fabric IP provides a flexible Network-on-Chip IP for high-performance SoCs and multi-chiplet designs, delivering high bandwidth, low latency, and built-in QoS and RAS. It natively connects AXI, APB, AXI-Lite, ACE-Lite, PCIe, HBM, DDR, and UCIe FDI interfaces through Baya’s scalable transport architecture.
Configured and optimized through FabricStudio, the fabric enables teams to explore topology, hierarchy, traffic patterns, and physical design constraints to meet bandwidth and latency targets while minimizing area and implementation risk. With support for advanced tiling, multicast, performance monitoring, and programmable QoS, it helps engineering teams build efficient, physically realizable non-coherent interconnects for scalable compute systems.
Key features
Native AMBA Non-Coherent Connectivity
Connect a wide range of AXI, APB, AXI-Lite, and ACE-Lite interfaces across CPUs, accelerators, PCIe controllers, memory controllers, coherent fabrics, and address-mapped peripherals.
High-Bandwidth Memory and I/O Integration
Enable efficient connectivity to PCIe, DDR, HBM, and UCIe-based die-to-die links with support for wide interfaces, multiple memory channels, and scalable high-throughput data movement.
Scalable Multi-Chiplet Architecture
Scale across up to 256 chiplets with flexible topology control, adaptive three-dimensional routing, and full topology customization through FabricStudio.
Performance Management and QoS
Use programmable bandwidth allocation, flow priority, route selection, input rate limiting, latency monitoring, and automatic QoS regulation to meet system-level performance goals.
Physically Aware, Deployment-Ready Design
Reduce implementation risk with advanced tiling, hierarchical design generation, RAS, debug, trace, performance monitoring, and PPA optimizations for scalable physical implementation.
Specifications
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Provider
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Frequently asked questions about NoC IP cores
What is Configurable AMBA Non-Coherent Fabric IP?
Configurable AMBA Non-Coherent Fabric IP is a Network-On-Chip IP core from Baya Systems listed on Semi IP Hub.
How should engineers evaluate this Network-On-Chip?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.