Automatic Generation of a Network-on-Chip Interconnect
This post discusses the network-on-chip (NoC) approach and explains how Agnisys can help you generate NoCs automatically for your designs.
Vendor:
Baya Systems
Category:
Network-On-Chip
Protocol-Neutral Custom Fabric
Flexible, software-defined fabric IP for custom protocols, AI workloads, and chiplet-scale systems.
Overview
Flexible, software-defined fabric IP for custom protocols, AI workloads, and chiplet-scale systems.
Our Protocol-Neutral Scalable Custom Fabric IP enables chip designers to build custom interconnects for advanced SoCs, AI accelerators, and chiplet-based systems using a flexible, protocol-independent transport fabric.
Designed for extreme flexibility, the fabric gives teams control over topology, routing, channel width, clock frequency, protocol clusters, and physical implementation choices. This allows engineering teams to optimize area, power, performance, and layout based on workload and floorplan requirements.
With built-in QoS, RAS, multicast, virtual channels, system-level simulation, and physically aware optimization through FabricStudio, the fabric helps teams create scalable custom architectures that support multiple protocols while reducing implementation risk and accelerating time to market.
Key features
Protocol-Neutral Transport
Create custom interconnects using a protocol-independent transport fabric that supports customer-defined protocols and enables multiple protocol domains to coexist within a unified architecture.
Extreme Bandwidth and Scalability
Scale to very high bandwidth and interface counts with up to 2048-bit channels, up to 64 parallel networks, and support for large multi-chiplet systems.
Flexible Topology and Protocol Clusters
Configure topology, routing, channel widths, clock frequency, and protocol-level clusters to match workload, floorplan, and system architecture needs.
AI-Optimized Multicast and Data Movement
Support high-throughput multicast, scatter/gather acceleration, deep virtual channels, and deterministic traffic behavior for demanding AI workloads.
Physically Aware, Deployment-Ready Design
Use FabricStudio-driven analysis, tiling, QoS, RAS, and performance monitoring to optimize implementation, reduce risk, and accelerate time to market.
Specifications
Identity
Part Number
Custom Fabric
Vendor
Baya Systems
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Network-On-Chip IP core
HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
Network-on-Chip (NoC) architectures have become the standard interconnect fabric for many-core systems, yet most proposals face a fundamental trade-off between latency, area, and congestion management. This paper presents HyNoC (Hybrid Network-on-Chip), an open-source NoC architecture that combines circuit-switch path establishment with wormhole data transfer, targeting distributed computing systems built around VLIW processor cores on FPGA.
Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures
Ensuring Network-on-Chip (NoC) security is crucial to design trustworthy NoC-based System-on-Chip (SoC) architectures. While there are various threats that exploit on-chip communication vulnerabilities, eavesdropping attacks via malicious nodes are among the most common and stealthy. Although encryption can secure packets for confidentiality, it may introduce unacceptable overhead for resource-constrained SoCs.
How Network-on-Chip Architectures Are Powering the Future of Microcontroller Design
Microcontrollers (MCUs) are no longer the humble workhorses of embedded systems. Today’s MCUs rapidly evolve into compact, high-performance computing platforms, integrating artificial intelligence (AI), advanced security features, and real-time processing into power-constrained environments.
Why verification matters in network-on-chip (NoC) design
In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.
SoC design: When a network-on-chip meets cache coherency
Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.
Frequently asked questions about NoC IP cores
What is Protocol-Neutral Custom Fabric?
Protocol-Neutral Custom Fabric is a Network-On-Chip IP core from Baya Systems listed on Semi IP Hub.
How should engineers evaluate this Network-On-Chip?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.