Configurable Cache Coherent Fabric IP
Scalable Coherent Connectivity for Advanced SoCs and Chiplet Systems
Overview
Scalable Coherent Connectivity for Advanced SoCs and Chiplet Systems
Advanced SoCs and chiplet-based systems need coherent fabrics that can efficiently connect CPUs, accelerators, memory, I/O, and peer-to-peer traffic while maintaining data consistency across the system. As coherent traffic scales across more agents, memories, and chiplets, the fabric must balance bandwidth, latency, cache coherency, QoS, and physical implementation requirements.
Baya’s Configurable Cache Coherent Fabric IP provides a scalable Network-on-Chip for systems where major traffic is coherent. It supports AMBA CHI interfaces for fully coherent agents, AXI interfaces for non-coherent and I/O-coherent agents, and ACE-Lite connectivity for I/O-coherent devices, enabling coherent, non-coherent, and peer-to-peer traffic to share a unified fabric architecture.
Configured and optimized through FabricStudio, the fabric gives teams flexible topology control, cache coherence controllers, built-in system-level cache, QoS, RAS, and physically aware implementation capabilities. It helps engineering teams build high-bandwidth, low-latency coherent interconnects that scale across advanced SoCs and multi-chiplet systems while reducing design risk and accelerating time to market.
Key features
Scalable Cache Coherent Architecture
Build cache-coherent fabrics across large SoCs and multi-chiplet systems with support for up to 256 chiplets, 128 HN slices, and flexible coherent topology control.
Flexible CHI, AXI, and ACE-Lite Connectivity
Connect fully coherent CHI agents, AXI-based system IP and memory controllers, ACE-Lite I/O-coherent devices, PCIe controllers, and non-coherent fabric through a unified system fabric.
System-Level Cache and Coherency Features
Support up to 512 MB of system-level cache, configurable snoop filters, UMA/NUMA/sub-NUMA modes, atomics, cache maintenance operations, and advanced coherency features.
Bandwidth Management and QoS
Use weighted bandwidth allocation, flow priority, virtual channel isolation, route selection, input rate limiting, and bandwidth/latency monitoring to meet system-level performance targets.
Physically Aware, Deployment-Ready Design
Enable modular implementation with advanced tiling, hierarchical design generation, RAS, debug, trace, ECC protection, runtime repair, and PPA optimizations for scalable physical design.
Specifications
Identity
Files
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Provider
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Frequently asked questions about Coherency Interconnect IP cores
What is Configurable Cache Coherent Fabric IP?
Configurable Cache Coherent Fabric IP is a Coherency IP core from Baya Systems listed on Semi IP Hub.
How should engineers evaluate this Coherency?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Coherency IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.