Vendor: Signature IP Corporation Category: PCI Express

Mesochronous Bridge for PCIe/CXL

Timing-Agnostic PCIe/CXL Bridge for Prototyping & Emulation

Overview

MesoLink™ is a plug-and-play soft IP that sits between a PIPE-compliant SerDes/PHY and a PIPE-compliant PCIe/CXL device under test, giving a timing-agnostic, transparent implementation of the DUT and a rapid path to SoC prototyping and emulation. It decouples DUT link width, PIPE width and clock from the system-side link, so the DUT runs at whatever PCLK it can close timing at while the system link stays at full rate. Link width is independent on each side — all 25 combinations of x1, x2, x4, x8 and x16 are supported, in either direction.

Key specifications

  • Protocols: PCIe, CXL
  • Interface: PIPE SerDes, both sides
  • Link widths: x1, x2, x4, x8, x16 — any combination, either direction
  • Link speeds: PCIe Gen1 through Gen6
  • Validated speed groups: Gen1–Gen2, Gen3–Gen5, Gen6
  • Flit mode: Configurable Gen1–Gen5, flit-only at Gen6
  • Max throughput: 8 GB/s per lane (Gen6)
  • Delivery: Soft IP — synthesizable RTL
  • Platform package: Siemens Veloce proFPGA CS (AMD VP1902)
  • Availability: Available now for licensing

Technical details

  • Link width: Independent per side — no constraint, any width to any width
  • PIPE width: Independent per side — must be legal for that side's link speed
  • Link speed: Independent within a validated speed group
  • Flit mode: Must match on both sides; Gen6 is flit-only, so the constraint is automatic at Gen6
  • DUT clock: PCLK is not tied to the system side or to the nominal frequency for its link speed
  • Throughput: Sustained bandwidth is bounded by the narrower or slower of the two links
  • Control: Configuration/register interface for link speed, lane width and bridge status
  • Gen1 (2.5 GT/s): 2 byte @ 125 MHz or 4 byte @ 62.5 MHz — 250 MB/s per lane
  • Gen2 (5 GT/s): 2 byte @ 250 MHz or 4 byte @ 125 MHz — 500 MB/s per lane
  • Gen3 (8 GT/s): 4 byte @ 250 MHz or 8 byte @ 125 MHz — 1 GB/s per lane
  • Gen4 (16 GT/s): 4 byte @ 500 MHz or 8 byte @ 250 MHz — 2 GB/s per lane
  • Gen5 (32 GT/s): 8 byte @ 500 MHz or 16 byte @ 250 MHz — 4 GB/s per lane
  • Gen6 (64 GT/s): 16 byte @ 500 MHz — 8 GB/s per lane

Key features

  • Any width to any width — all 25 combinations of x1 / x2 / x4 / x8 / x16
  • DUT runs at its own PCLK, independent of the system side
  • Timing-agnostic — the system link stays at full rate
  • PIPE SerDes interface on both sides
  • Asymmetric PIPE width, lane count and link speed, configured per side
  • Throughput follows the slower side, by design
  • PCIe Gen1 through Gen6, flit and non-flit
  • Delivered as synthesizable RTL
  • Packaged for the Siemens Veloce proFPGA CS platform

Block Diagram

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Specifications

Identity

Part Number
MesoLink™
Vendor
Signature IP Corporation
Type
Silicon IP

Provider

Learn more about SignatureIP's MesoLink IP core

Frequently asked questions about PCIe IP cores

What is Mesochronous Bridge for PCIe/CXL?

Mesochronous Bridge for PCIe/CXL is a PCI Express IP core from Signature IP Corporation listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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