Vendor: Logic Design Solutions Category: I2C / I3C

I2C MAster Slave

The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus.

Overview

The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried out on a byte-wise basis using interrupt or polled handshake. It controls all I2C-bus specific sequences, protocol, arbitration and timing. The I2C macro interface allows the parallel-bus microprocessor to communicate bidirectionnally with the I2C-bus.This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.

Key features

  • Single-chip synchronous I2C Master and Slave Macro in FPGA (I2C is a trademark of Philips, Inc)
  • Designed to be included in high-speed and high-performance applications
  • Direct Connection to CPU register set
  • Compliant with I2C-bus specification version 1.0
  • Standard mode operation (100Kbits)
  • Multi-master operation with arbitration and clock synchronisation (only master)
  • Support for reads and writes only
  • 7-bit and 10-bits address management
  • Synchronised on system clock
  • Hardware digital filter on SCL and SDA signals
  • No support of general call
  • FPGA speed grade operating frequency dependant : system clock up to 180 MHz
  • Available in VHDL source code format for ease of customization
  • Can be customised by Logic Design Solutions

What’s Included?

  • VHDL Source code
  • VHDL Test Bench for behavioural and gate level simulation.
  • Data Sheet and Reference Guide
  • User’s guide : Simulation, Synthesis and Place and Route procedures.
  • Constraint File

Specifications

Identity

Part Number
MI2CMS
Vendor
Logic Design Solutions
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Frequently asked questions about I2C / I3C IP cores

What is I2C MAster Slave?

I2C MAster Slave is a I2C / I3C IP core from Logic Design Solutions listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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