What is Synchronous Universal Asynchronous Receiver/Transmitter?
Synchronous Universal Asynchronous Receiver/Transmitter is a UART IP core from Logic Design Solutions listed on Semi IP Hub.
Vendor:
Logic Design Solutions
Category:
UART
Synchronous Universal Asynchronous Receiver/Transmitter
The macro MUART, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a micr…
Overview
The macro MUART, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a microprocessor and a serial communication channel.
This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
This macro can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
Key features
- Single-chip synchronous UART
- Designed to be included in high-speed and high-performance applications
- Very fast system clock frequency (FPGA speed grade dependant)
- CPU independent interface
- Complete asynchronous communication protocol including :
- 5,6,7 or 8-bit data transmission
- Even/Odd or no parity bit generation and detection
- Start and Stop bit generation and detection
- Line break generation and detection
- Receiver Overrun and framing detection
- High baud rate (system frequency dependent)
- 1 to 65535 divisor generates 16X clock
- Register and FIFO mode
- Buffered transmit and receive registers
- Transmitter and receiver are buffered with 16 Byte FIFO, plus 3 error bits per data byte on receiver
- Polled or interrupt mode
- Loopback mode
- DO254 Documentation available
What’s Included?
- VHDL Source code
- VHDL Test Bench for behavioural and gate level simulation.
- Data Sheet
- Reference Guide
- User’s guide : Simulation, Synthesis and Place and Route procedures.
- Constraint File
Specifications
Identity
Part Number
MUART
Vendor
Logic Design Solutions
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
FRANCE
Frequently asked questions about UART IP cores
How should engineers evaluate this UART?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UART IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.