Vendor:
Logic Design Solutions
Category:
SPI / QSPI XSPI
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI sla…
Overview
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can be programmed to run either in standard SPI mode where bidirectional one byte transactions are implemented, or in extended SPI mode where frame transactions are implemented as an SPI EEPROM Controller. The MSPIM IP controls all SPI-bus specific sequences, protocol and timing. This IP can be customized according to specific needs (application-specific requirement). Any other pre-designed functions can be integrated into the FPGA. FPGA density and I/O requirements can be defined according to customer specification.
Key features
- Single-chip synchronous SPI Master IP in FPGA
- Designed to be included in high-speed and high-performance applications
- Direct Connection to CPU register set
- High frequency rate
- Two run-time mode : Standard SPI mode and Extended SPI mode as SPI EEPROM controller
- Synchronised on system clock
- Serial clock programmable with polarity and phase
- Serial clock period can be at least 6 system clock period
- FPGA speed grade operating frequency dependant
- Available in VHDL source code format for ease of customization
- DO254 documentation available
- Can be customized by Logic Design Solutions
What’s Included?
- VHDL Source code
- VHDL Test Bench for behavioural and gate level simulation.
- Data Sheet
- Reference Guide
- User’s guide
- Simulation, Synthesis and Place and Route procedures.
- Constraint File
Specifications
Identity
Part Number
MSPIM
Vendor
Logic Design Solutions
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
FRANCE
Learn more about SPI / QSPI XSPI IP core
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Frequently asked questions about SPI / QSPI / xSPI IP cores
What is SPI Master - EEPROM Controller?
SPI Master - EEPROM Controller is a SPI / QSPI XSPI IP core from Logic Design Solutions listed on Semi IP Hub.
How should engineers evaluate this SPI / QSPI XSPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.