TSMC CLN5FF GLink 2.0 Die-to-Die PHY
IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC packaging solutions: Integrated Fan-Out (InF…
- TSMC
- 5nm
- N5FF
- Available on request
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
TSMC CLN5FF GLink 2.0 Die-to-Die PHY
IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC packaging solutions: Integrated Fan-Out (InF…
TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC packaging solutions: Integrated Fan-Out (In…
I2C Controller IP – Slave, Parameterized FIFO, AHB Master Interface (I2C2AHB)
The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I2C Controller IP – Slave, Parameterized FIFO, AXI Master Interface (I2C2AXI)
The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I2C Controller IP – Slave, Parameterized FIFO, APB Master Interface (I2C2APB)
The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
DO-254 compliant MIL-STD-1553B IP core
MIL-STD-1553B IP Core implements MIL-STD-1553B standard and provides single or multi-functional interface between host processor …
Receives video data from Flir's Lepton IR-sensors, Video over SPI (VoSPI)
To transfer the sensor data with minimal software and hardware, FLIR has developed the VoSPI protocol, an SPI based Video Interfa…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
Silicon agnostic implementation of the structure agnostic mapping method described in the IEEE 1914.3 standard The Radio Over Eth…
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver
The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
Silicon Proven 1G Ethernet PHY IP as Whitebox
1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to…
MIPI D-PHY Transmitter/Receiver for TSMC 22nm ULL
The MIPI® D-PHY Transmitter/Receiver is useful 2 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of TSMC 22nm ULL process.
MIPI D-PHY Transmitter/Receiver for Samsung 28nm FD-SOI
The MIPI® D-PHY Transmitter/Receiver is useful 4 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of Samsung 28nm FD-SOI process.
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
The MIPI® D-PHY Transmitter/Receiver is useful 2 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of TSMC 40nm LP process.
BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.
Silicon agnostic Ethernet MAC IP for 40G, 100G speeds Ethernet MAC 40G/100G IP is a solution that enables the host to communicate…
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter
The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps.
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 supporting…
16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provid…
The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process.