Overview
A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data transfers while using less power. A specific design for USB 3.1 type-C applications is the USB 3.1Type-C PHY IP. A separate PCS can be provided in addition to the USB 3.1 Type C PHY IP to complete the functionality of various applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control, and testing. Depending on the customer's request, PCS is offered as either a hard macro or a soft macro. The PCS standard will also be made accessible independently. A test bench created in Verilog HDL is used to validate PHY functionality by the NC-Verilog simulation program.
Learn more about Single-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
