Vendor: Nextera Video Category: Video Transport

IPMX Encoder and Decoder

IPMX is the emerging AV over IP standard for use in Professional AV.

Overview

IPMX is the emerging AV over IP standard for use in Professional AV. Based on the widely adopted and proven ST 2110 standard with NMOS control software, IPMX finally makes AV over IP truly interoperable.

IPMX offers the following capabilities:

- Compressed Video (4Kp60 over 1G)
- Asynchronous Video (No need for PTP generators)
- Industry Standard Control (NMOS)

As well as other ProAV requirements such as:

- HDCP
- EDID
- General Purpose I/O

Key features

  • TR-08 Compliant (requires JPEG-XS Core)
  • Included IPMX support for:
    • TR-10-1 (System Timing)
    • TR-10-2 (Video)
    • TR-10-3 (Audio)
    • TR-10-4 (Ancillary)
    • TR-10-8 (NMOS)
    • Networks with and without a Common Clock Reference
  • Fully integrated and modular solution
  • ST 2110 and NMOS base cores have been interop tested and proven in Broadcast TV
    • www.jt-nm.org/jt-nm-tested
  • Video/Audio Specs
    • Uncompressed & Compressed (JPEG-XS, etc.)
    • Format and Frame Rate Independent
      • Any Resolution: Video/Computer up to 8K+
      • Any Network: 1G, 2.5G, 5G, 10G, and 25G+
      • Any Color Space: RGB or YCbCr (w/ Key)
      • Any Color Sampling: 4:4:4, 4:2:2, or 4:2:0
      • Any Bit Depth: 8, 10, 12, or 16 bit
    • Audio Sample Rate Independent
    • Programmable Packet Time
    • L16, L20, L24, AES3 Audio

What’s Included?

  • Delivered as RTL IP Cores, including all PetaLinux software drivers, daemons, system control software, and a Web GUI, along with:
    • Product Guides
    • Application Note
    • HDMI I/O Demo Design for:
    • Zynq UltraScale+ ZCU106 (1G or 10G)

Specifications

Identity

Part Number
IPMX
Vendor
Nextera Video
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is IPMX Encoder and Decoder?

IPMX Encoder and Decoder is a Video Transport IP core from Nextera Video listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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