Scalable Ultra-High Throughput VESA DSC 1.2b Encoder

The UHT-DSC-E core is an advanced video encoder IP, compliant to the VESA Display Stream Compression (DSC) v1.2b standard. It supports encoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits sample depths.

The core is scalable and has been designed for enabling ultra-high throughput video encoding, even in medium-range target implementation technologies. It is available for ASIC and AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.

The UHT-DSC-E is designed using internal (on-chip) memory blocks only, with simple and fully controllable streaming input and output interfaces. It is a complete and autonomous encoder, not needing any host system CPU or GPU support for its operation. Being carefully designed and rigorously verified, the UHT-DSC-E is a reliable and easy-to-use and integrate IP core.

• VESA DSC 1.2b Compliant, Complete and Standalone Operation
  • Full compliance with the VESA DSC 1.2b specification
  • Backwards compatible with VESA DSC 1.1
  • Visually lossless compression for all types of content
  • All DSC 1.2b encoding mechanisms supported
    • MMAP, BP, MPP and ICH
  • RGB and YCbCr input formats
  • 8, 10, 12, 14 and 16 bits per color component dynamic range
  • Native support for 4:4:4, 4:2:2 and 4:2:0 sampling formats
  • Integrated bit accurate rate control
    • CBR or VBR mode of operation
  • Up to 16 slices per line
  • Scalable architecture with configurable number of internal, parallel encoding engines
    • 1 pixel/clock per encoding engine processing for 4:4:4 sampling format
    • 2 pixels/clock per encoding engine processing for 4:2:2 and 4:2:0 sampling formats
  • Operation without external memory
    • Very low internal memory requirements (a few image lines)
  • Ultra-low latency performance (sub-line latency)
  • CPU/GPU-less, complete and standalone HW implementation
• Trouble-Free Technology Map and Implementation
  • Self-contained RTL design
  • No internal tri-states
  • Strictly positive edge triggered design
  • D-type only Flip-Flops
  • Fully synchronous operation per clock domain
  • Safe CDC transfers between clock domains
  • No need for special timing constraints
    • No false or multi-cycle paths within the same clock domain
    • No CDC transfers that need to be specially constrained
    • No other specially constrained timing paths

• Clear text VHDL RTL source for ASIC designs, or pre-synthesized and verified Netlist for Intel, Lattice, Microsemi and Xilinx FPGA and SoC devices
• Extensive documentation
• Bit Accurate Model (BAM) with optional Test Vector generation functionality
• Self-checking testbench environment
• Sample BAM scripts
• Synthesis scripts
  • Simulation scripts
  • Place & Route scripts for FPGAs