TSMC N3E SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
- TSMC
- 3nm
- N3E
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
TSMC N3E SD/eMMC PHY North/South Poly Orientation
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.
ARINC 429 IP Core implements ARINC 429 standard.
MIPI DSI DisplayTransmitter IP
MIPI DSI Transmitter IP is designed to transmit the data to the host processor.
MCU-less USB Billboard Device Controller
The CT25100 is a Full-Speed USB controller, which enumerates as Billboard Device.
SOF-Calibrated 48MHz USB Clock
CT20101 is an auto calibrating oscillator delivering a precise 48 MHz clock frequency required by any USB1.1 or USB2.0 low and fu…
USB Power Delivery 3.1 Physical Layer
CT20602 is a USB Power Delivery 3.1 Physical Layer.
CT20601 is a USB Type-C Interface which includes optional VCONN and VBUS management features.
Industry First, Silicon Proven, 116 Gbps per lane IP core, backed by a portfolio of verification tools, PHY interop, and demos Th…
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on ea…
The Camera Link® IP Core is a high-speed LVDS transmitter / receiver pair that conforms to the standard Camera Link protocol orig…
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP
The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 55SP
The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
V-by-One Rx IP, Silicon Proven in 40G
Using internal equipment connections, the V-by-One HS technology seeks to send video signals at a high data rate.
V-by-One Tx IP, Silicon Proven in 40G
The V-by-One HS technology aims to transmit video signals at a high data rate using an internal connection between devices.
V-by-One/LVDS Tx Combo PHY, Silicon Proven in 28HPC+
V-by-One/ LVDS Tx Combo PHY IP Core aims at achieving high-speed data transmission for video signals through internal equipment c…
Power Management IC - I3C Basic Interface IP
Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application.
OPEN Alliance TC6 10BASE-T1S MACPHY Interface
The CT25209 Digital IP core implements the MACPHY SPI protocol defined by the “OPEN Alliance TC6 Serial 10BASE-T1x MACPHY Interfa…
The CT25208 Digital IP core is a standard Clause 4 CSMA/CD MAC exposing a proprietary, FIFO-like MAC Client interface (TX/RX).
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF
The GPHY is a integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption.