Flexibilis Redundant Switch - 3 to 8 Port Ethernet IP with HSR/PRP
Flexibilis Redundant Switch (FRS) is an IP core providing HSR/PRP functionality.
- Ethernet
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Flexibilis Redundant Switch - 3 to 8 Port Ethernet IP with HSR/PRP
Flexibilis Redundant Switch (FRS) is an IP core providing HSR/PRP functionality.
CameraLink IP for high speed, real-time, high bandwidth applications
CameraLink is the best suited interface standard for real time, low latency, high bandwidth applications.
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design
The DB-I3C-BASIC-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI …
TSMC CLN6FF/7FF Die-to-Die Interface PHY
This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps o…
This is a implementation of a 16550 UART.
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash co…
AHB-Lite to AHB-Lite Asynchronous Bridge
The AHB-Lite to AHB-Lite Asynchronous Bridge translates an AHB-Lite bus transaction (read or write) on one clock domain to an AHB…
CXL Host Device Dual mode controllers
Primesoc's CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.
The USB 2.0 Hub IP core provides a link between the USB2.0 Host and multiple USB peripherals via UTMI + Low pin interface (ULPI).
Super Speed USB 3.0 Extensible Host Controller xHCI
USB3.0 Super-Speed Host The Super-Speed USB Host Controller is designed for flexibility, ease of use and provides ASIC/FPGA desig…
UDP/IP – 1 GbE Protocol Hardware Stack
The DB-UDP-IP-1GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 1 GbE…
UDP/IP – 10 GbE Protocol Hardware Stack
The DB-UDP-IP-10GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 10 G…
UDP/IP – 25 GbE Protocol Hardware Stack
The DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 25 G…
UDP/IP – 40 GbE Protocol Hardware Stack
The DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 40 &…
UDP/IP – 50 GbE Protocol Hardware Stack
The DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 50 G…
10M/100M/1G/10G/25G Unmanaged Ethernet Switch
Silicon-Agnostic, Compact and flexible Ethernet Switch IPs Unmanaged Ethernet Switch IP cores are a family of Ethernet switching …
The eSi-I2C core implements the I2C two-wire protocol.
APB SPI (Serial Peripheral Interface) master and slave
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications b…
APB UART with optional ISO7816-3
The eSi-UART core can be used to implement asynchronous serial communications.
The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream.