Vendor: T2M GmbH Category: Single-Protocol PHY

USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++

A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.

USB 2.0 View all specifications

Overview

A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP. The USB2.0 IP implements the High-Speed USB 2.0 transceiver, which can be used with hosts, devices, or OTG function controllers. The USB2.0 PHY IP, which supports both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates, comes after the UTMI+ level 3 specification. 480Mbps of high-speed data can be transferred by combining numerous mixed-signal circuits. The enhanced USB Battery Charging standards, which are designed for mobile and consumer product applications, are also supported by the USB2.0 PHY IP. Small chip size and low power consumption of the USB2.0 PHY IP transceiver did not compromise performance or data throughput. The USB2.0 PHY IP contains a full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit in order to fully enable host and device functionality.

Key features

  • Compliant with USB2.0 and USB1.1 specification
  • Compliant with UTMI Specification Version level 3.
  • Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
  • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
  • 16-bit, 30MHz or 8-bit, 60MHz parallel interface for HS/FS
  • Serializing for transmitting data stream and Deserializing for receiving data stream
  • USB Data Recovery and Clock Recovery on receiving
  • Integrated Bit Stuffing and NRZI encoding for Transmit
  • Integrated Bit Un-Stuffing and NRZI decoding for Receive
  • SYNC and EOP generation on transmit packets and detection on receive packets
  • Internal reference resistor that replaces the external reference resistor
  • Built in self test for production testing
  • Supports USB suspend state and remote wakeup
  • Supports detection of USB reset, suspend and resume signaling
  • Supports high speed identification and detection as defined by USB 2.0 Specification
  • Support high speed host disconnection detection
  • Silicon Proven in SMIC 12SF++

Block Diagram

USB 2.0 PHY IP in 12SF++ block diagram

What’s Included?

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Specifications

Identity

Part Number
USB 2.0 PHY IP in 12SF++
Vendor
T2M GmbH
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 2.0

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++?

USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++ is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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