The TCPIP-1G/10G core implements a TCP/IP Hardware Protocol Stack.
- Ethernet
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The TCPIP-1G/10G core implements a TCP/IP Hardware Protocol Stack.
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 40LP
Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.
HomePlugAV is a new standard designed to provide the high data rates and guaranteed Quality of Service (QoS) required by today’s …
Super-Speed Plus USB 3.2 Hub Controller
USB3.2 SuperSpeed Hub The Super Speed Plus USB bus is implemented as a separate dual-simplex dual lane data path consisting of tw…
Universal Chiplet Interconnect Express (UCIe™) PHY and Controller
High-bandwidth, low-power and low-latency standardized die-to-die interconnect
USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 12SF++
A high performance, high-speed SERDES IP known as USB3.1Type-C PHY was created for semiconductors that allow high bandwidth data …
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 12SF++
Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PIPE int…
USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++
A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG
A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization.
IPMX is the emerging AV over IP standard for use in Professional AV.
DisplayPort Transmitter & Receiver
Logic Fruit Technologies has introduced DISPLAY PORT Transmitter and Receiver IP Cores, adhering to Display Port 2.0/eDP1.5 stand…
Configurable MAC solutions for speeds from 10Gbps to 25Gbps
The MIPI C-PHY IPis a high-frequency, low-power, low cost, physical layer.
Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
The UHT-DSC-D core is a scalable, ultra-high throughput, DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC)…
Scalable Ultra-High Throughput VESA DSC 1.2b Encoder
The UHT-DSC-E core is an video encoder IP, compliant to the VESA Display Stream Compression (DSC) v1.2b standard.
JESD204C Transmitter and Receiver
Logic Fruit Technologies has developed a JESD204C RTL IP supporting lane rates up to 32 Gbps for high-bandwidth applications.
JESD204B Transmitter and Receiver
The vendor has developed the JESD204B RTL IP, supporting lane rates up to 12.5 Gbps for high-bandwidth applications.
The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.
TSMC CLN7FF GLink-3D Die-to-Die Slave PHY
IGAD2DX03A is a GLink-3D high speed die-to-die interface Slave PHY.
TSMC CLN5FF GLink-3D Die-to-Die Master PHY
IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY.