The T40LP_MIPIDPHYV01 IP is a MIPI D-PHY and LVDS based on TSMC 40nm LP process.
- MIPI D-PHY
- TSMC
- 40nm
- LP eFlash
- Available on request
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The T40LP_MIPIDPHYV01 IP is a MIPI D-PHY and LVDS based on TSMC 40nm LP process.
The IP is a USB PHY based on TSMC 180nm process.
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018 The Ethern…
Smart card controller core is compliant to ISO 7816 3 specification.
The Ethernet MAC and PCS 10G/25G is a silicon agnostic implementation of the IEEE 802.3 standard.
Networking SerDes IP, Silicon Proven in ST 28FDSOI
The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling…
LVDS Rx IP, Silicon Proven in GF 28LPe
A physical layer IP for LVDS Receiver.
Display Port 1.4 Rx PHY & Controller IP (Silicon Proven in IDM 180nm /150nm)
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in ST 28FDSOI
The HDMI receiver PHY (Physical layer), a single-port IP core, complies with all the specifications of HDMI 1.4.
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI
IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY provides a…
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 130/110G
IP core for physical layer HDMI transmitters that fully complies with HDMI 1.4 specifications The HDMI transmitter PHY supports p…
MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY
MIPI DSI transmitter IP is used to connect to up to two displays using the MIPI DSI-1 protocol.
MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels.
MIPI CSI-2 Receiver v1.1 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels.
USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)
A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data c…
PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
The Peripheral Component Interconnect Express Gen3 PHY IP with PIPE 4.3 interface standard supported by this that complies with P…
MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection
The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication.
Gigabit Ethernet PHY (Modification Right)
Gigabit Ethernet PHY Modification Right (in production)
CPU-less QUIC Offload IP core for FPGA Acceleration
QUIC Client 10Gbps IP Core (QUIC10GC-IP) is engineered from the ground up to simplify the QUIC protocol with TLS 1.3 security int…