Overview
Serial ATA (SATA) compliant with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PIPE interface protocol, and USB compliant with USB 3.0, USB 2.0, make up the combo PHY (USB High-speed and Full speed). Lower power consumption is achieved by supporting additional internal power gating, reference clock control, and PLL control. Due to the flexible nature of the aforementioned low power mode option, the PHY is also extremely beneficial for a variety of situations under different considerations of power consumption.
Learn more about Multi-Protocol PHY IP core
It is very important that the design aspects of the NB-IoT device protocol stack ensure low module cost and low energy consumption. This is required to match the industry expected module costs. This paper outlines some of the NB-IoT Protocol stack specification flexibilities and generic design aspects that are to be considered to meet the above requirements, especially with reference to LTE.
