PHY and SerDes IP cores are essential building blocks for high-speed data transmission in modern semiconductor designs. This category includes physical layer IP and serializer/deserializer solutions used to implement reliable chip-to-chip, die-to-die, backplane and interface connectivity across networking, compute, storage, automotive and consumer applications.
Browse PHY / SerDes semiconductor IP for high-speed interfaces requiring robust signal integrity, scalable lane configurations, low power and standards-oriented interoperability. Compare controller-adjacent PHY IP, generic SerDes architectures and specialized high-speed connectivity solutions from multiple vendors for integration into ASICs, SoCs and advanced package designs.
Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
Intel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targe…
Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…
Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
The Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible …
40G Ethernet MAC and PHY FPGA IP Core
The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.
1G/10Gb Ethernet PHY Intel® FPGA IP
The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…
Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V LVDS Transceiver.
Best in class MIPI® M-PHYsm Verification IP for your IP, SoC, and, System-level Design Testing In production since 2011 on dozens…
Simulation VIP for MIPI D-PHY, C-PHY and A-PHY
Cadence provides a mature and comprehensive Verification IP (VIP) for the D-PHY/C-PHY/A-PHY, which is part of the MIPI family.
The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for hi…
4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
OT3910bjc is a set of cells designed for implementing the transmitter, receiver and associated bias function for LVDS point to po…
Compatible with embedded display port v1.5/v1.4b specification; Four-lane main link with support for 8.1/5.4/4.32/3.24/2.7/2.43/2.16/1.62Gbps
Compliant with ONFI 5.1 specification; Supports NV-DDR3/NV-LPDDR4, with a maximum rate up to 3600MT/s; Supports matched or unmatched DQS
MIPI C/D Combo TX PHY and DSI controller
The MIPI C and D Combo Transmitter PHY and DSI Controller are tailored for high-performance display applications.
MIPI D-PHY TX PHY and DSI controller
The MIPI D-PHY Transmitter PHY and DSI Controller are tailored for high-performance display applications.
Our LVDS (Low Voltage Differential Signaling) and OpenLDI (Open Low-voltage Differential Signaling Interface) PHY which is compos…
The HDMI 2.0 TX (Transmitter) is a multimedia interface designed to deliver high-definition video and audio from source devices t…
The Embedded DisplayPort (eDP) 1.3 Transmitter PHY is a high-performance interface IP designed to enable the transmission of vide…