Vendor: MSquare Category: Single-Protocol PHY

ONFI 5.1 PHY IP

MSquare's ONFI 5.1 PHY is a high-performance and low-power PHY IP, which supports all modes of the Open NAND Flash Interface (ONF…

Contact Provider Request Datasheet

Overview

MSquare's ONFI 5.1 PHY is a high-performance and low-power PHY IP, which supports all modes of the Open NAND Flash Interface (ONFI) 5.1 specification. ONFI is an interface connecting external flash particles (NAND Flash) and internal flash controller (NAND Controller), widely used in Solid State Drive (SSD) products. To simplify the implementation, MSquare ONFI 5.1 PHY supports expandable channels and customizable CE/RB pad numbers. 

Key features

  • Compliant with ONFI 5.1 specification
  • Supports NV-DDR3/NV-LPDDR4, with a maximum rate up to 3600MT/s
  • Supports matched or unmatched DQS
  • Supports WDCA/Per-Pin VREFQ Training for NAND devices
  • Supports WT Monitor
  • Supports Separate Command Address (SCA) to improve NAND IO efficiency
  • Supports 2 channels with a single PHY PLL & flexible floorplan with double or single row IO
  • Supports DFI with 1:1 / 1:2 clock ratio mode
  • Supports TX/RX Training mode
  • Delay-Chain supports background tracking for PVT compensation
  • Test Mode: Self-test mode with built-in BIST & Loopback test with built-in PRBS & BIST-Delay-Chain

Block Diagram

ONFI 5.1 PHY block diagram

Specifications

Identity

Part Number
ONFI 5.1 PHY
Vendor
MSquare
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

MSquare
HQ: China
Contact MSquare

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is ONFI 5.1 PHY IP?

ONFI 5.1 PHY IP is a Single-Protocol PHY IP core from MSquare listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP