Vendor: Cadence Design Systems, Inc. Category: MIPI PHY

Simulation VIP for MIPI M-PHY

Best in class MIPI® M-PHYsm Verification IP for your IP, SoC, and, System-level Design Testing In production since 2011 on dozens…

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Verification IP MIPI M-PHY View all specifications

Overview

Best in class MIPI® M-PHYsm Verification IP for your IP, SoC, and, System-level Design Testing

In production since 2011 on dozens of production designs.

Incorporating the latest protocol updates, the mature, highly capable Cadence Verification IP (VIP) for the MIPI® M-PHYsm Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. It includes highly configurable and flexible simulation models of all the protocol layers, devices, and transaction types.

Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for M-PHY helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM). It supports integration and traffic generation in all popular verification environments.

Supported specification: MIPI M-PHY specification v4.0, v4.1, v5.0 and v6.0.

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Specification compliance
  • Complies with MIPI M-PHY 4.0, 4.1, 5.0 and 6.0 specification

M-PHY type 1 and type 2
  • Supports type 1 and type 2

M-PHY interface
  • Supports serial interface (DpDn) and signaling interface (RMMI)

M-PHY modes
  • Supports burst state, ACTIVATED SAVE states (SLEEP and STALL), and hibernate (“HIBERN8”) state

M-PHY transmission modes
  • Supports multiple transmission modes with different bit-signaling and clocking schemes
  • Supports multiple transmission speed ranges (PWM G1-G7, HS G1 - HS G6) and rates per BURST mode

Multi-lane
  • Supports distribution and merging data over one to four lanes, also supports a different number of lanes per sub-link (direction)

Test mode
  • Support for test mode functionality including loop-back mode

CDR
  • Supports clock data recovery

PAM4
  • Supports PAM4 signaling mechanism

HS-G6 with 1b1b encoding
  • Supports HS-G6 data rate with 1b1b encoding

PAM-4 Signal Chain Coding
  • Supports Scrambling, Gray coding and Pre coding

Block Diagram

Simulation VIP for MIPI M-PHY block diagram

Benefits

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Compliance: Contains predefined checks to verify that the DUT adheres to the protocol rules defined in the M-PHY Specification
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive coverage in SystemVerilog
  • Packet tracker creation for easy debugging

Specifications

Identity

Part Number
Simulation VIP for MIPI M-PHY
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Standards & Interfaces

MIPI PHY
MIPI M-PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

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Frequently asked questions about MIPI PHY IP

What is Simulation VIP for MIPI M-PHY?

Simulation VIP for MIPI M-PHY is a MIPI PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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