Vendor: InPsy Category: Single-Protocol PHY

eDP 1.3 Transmitter PHY

The Embedded DisplayPort (eDP) 1.3 Transmitter PHY is a high-performance interface IP designed to enable the transmission of vide…

Overview

The Embedded DisplayPort (eDP) 1.3 Transmitter PHY is a high-performance interface IP designed to enable the transmission of video and audio signals in embedded applications. Optimized for use in devices such as laptops, tablets, all-in-one PCs, and high-resolution displays, the eDP 1.3 Transmitter delivers exceptional video quality and power efficiency, ensuring a superior user experience for modern multimedia applications.

Key features

  • Fully compliant to VESA Embedded DisplayPort 1.3 specifications
  • Support Embedded DisplayPort RBR, HBR, and HBR2 data rate and customized data rate
  • Configurable x1/x2/x4 Main-Link data lanes
  • PIPE SerDes Mode interface to Embedded DisplayPort controller
  • Main link transmitter supports eDP pre-emphasis feature
  • Supports three PIPE data width options: 10-bit, 20-bit and 40-bit
  • Built-in scrambling and ANSI 8b/10b encoding blocks
  • PLL support SSC function

Specifications

Identity

Part Number
eDP 1.3 Transmitter PHY
Vendor
InPsy
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

InPsy
HQ: Taiwan (R.O.C.)

Learn more about Single-Protocol PHY IP core

InPsytech showcases 3nm UCIe 3.0 technology at OCP 2025, Accelerating Innovation in Chiplet Ecosystem

InPsytech has long focused on high-speed and low-power interface IP technologies. Its UCIe (Universal Chiplet Interconnect Express) portfolio supports advanced process nodes from 22nm down to 2nm, optimized for 3nm production. The IP achieves data transfer rates up to 64 GT/s, while supporting 2.5D and 3D packaging architectures to enable high-efficiency chip-to-chip interconnects and heterogeneous integration.

Frequently asked questions about Single-Protocol PHY IP

What is eDP 1.3 Transmitter PHY?

eDP 1.3 Transmitter PHY is a Single-Protocol PHY IP core from InPsy listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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