PHY and SerDes IP cores are essential building blocks for high-speed data transmission in modern semiconductor designs. This category includes physical layer IP and serializer/deserializer solutions used to implement reliable chip-to-chip, die-to-die, backplane and interface connectivity across networking, compute, storage, automotive and consumer applications.
Browse PHY / SerDes semiconductor IP for high-speed interfaces requiring robust signal integrity, scalable lane configurations, low power and standards-oriented interoperability. Compare controller-adjacent PHY IP, generic SerDes architectures and specialized high-speed connectivity solutions from multiple vendors for integration into ASICs, SoCs and advanced package designs.
MIPI C-PHY℠ v2.0 + D-PHY℠ v2.5 Combo IP Core
This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…
The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself …
The MIPI C/D-PHY combo IP is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for …
Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and receptio…
GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs.
PCIe Gen 6 Phy
A 2Gbps LVDS Tranceiver in TSMC 28nm This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power …
2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
A 2Gbps differential transceiver.
USB3.1 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…
SATA/SAS 3.0 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and …
With sophisticated architecture and technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high perfo…
With sophisticated architecture and technology, the multi-mode transceiver IP with PMA and PCS layer is designed for low power an…
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.
High-speed LVDS (Low-Voltage Differential Signaling) transceiver
This IP is a high-speed LVDS (Low-Voltage Differential Signaling) transceiver supporting multi-channel joint.
Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES Receiver on TSMC CLN65LP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
Programmable Low Power SERDES on TSMC CLN28HPL
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen5 SERDES PHY on Samsung 8LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).