Vendor: Certus Semiconductor Category: Single-Protocol PHY

LVDS Transceiver in TSMC 28nm

A 2Gbps LVDS Tranceiver in TSMC 28nm This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power …

Overview

A 2Gbps LVDS Tranceiver in TSMC 28nm

This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity. Engineered with 1.8V thick oxide devices and a 0.8V standard core interface, it operates ef- ficiently across a wide temperature range (-40°C to 125°C). The transceiver supports data rates up to 2Gbps, offering low jitter, robust ESD protection (+2kV HBM, +500V CDM), and integrated on-die termination for enhanced noise immunity. Opti- mized for applications requiring precision and reliability, this LVDS I/O solution ensures clean, high-speed data transmission ideal for imaging systems, communication interfaces, and high-performance computing.

Operating Conditions

Parameter Value
Devices 1.8V Thick and 0.9V Thin Oxides
BEOL 8 Metals Min.
VDDIO 1.8V
VDD 0.8V
Temperature -40C to 125C
ESD +2kV HBM, +500V CDM

Key features

  •  2Gbps transmit and receive modes
  •  Available 100 ohm on-die termination
  •  Selectable pre-emphasis for high speeds at heavier loads
  •  +2kV HBM & +500V CDM protection
  •  Input and output disable

Block Diagram

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm —

Specifications

Identity

Part Number
LVDS28
Vendor
Certus Semiconductor
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: United States

Learn more about Single-Protocol PHY IP core

CDM Dependence on Device Capacitance

This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.

Field Induced CDM Explained

Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.

One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies

Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.

Frequently asked questions about Single-Protocol PHY IP

What is LVDS Transceiver in TSMC 28nm?

LVDS Transceiver in TSMC 28nm is a Single-Protocol PHY IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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