Vendor: Altera Category: Multi-Protocol PHY

GTS PMA/FEC Direct PHY IP

GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs.

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Overview

GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs. The transceiver is monolithically integrated into the FPGA core fabric offering up to 28Gbps for Agilex™ 5 and up to 12.5Gbps data speeds for Agilex™ 3 FPGA. The transceiver is optimized for power efficiency, low-latency, and dynamic reconfiguration to implement multiple protocols.

*Only in Agilex™ 5 FPGA E-Series Group A and D-Series devices

**Only in Agilex™ 3 FPGA C-Series

Key features

  • Dynamic Reconfiguration - NRZ transceivers optimized for a wide variety of applications, ranging from 1 Gbps to 28.1 Gbps* and 1 Gbps to 12.5Gbps**
  • Advanced adaptive equalization circuits to enable long-reach backplane driving applications.
  • Dedicated PMA and PLLs for independent usage of transceiver channels with Avalon® memory-mapped interface.
  • Hardened PCS—supports 64b/66b encoding and decoding functions, data scrambling, block alignment, and gear boxing functions.
  • Hardened FEC—Firecode and Reed Solomon for 10/25 Gb Ethernet BASE-KR/CR (Backplane) applications.
  • Supports SFP and SFP+ Direct Attach for implementation of optical modules.
  • Supports PCIe 4.0 x8*, PCIe 3.0 x4**, 25Gb Ethernet*, and 10Gb Ethernet** with IEEE 802.3 compliant, and FEC – Firecode and Reed Solomon.

Block Diagram

GTS PMA/FEC Direct PHY IP block diagram

Applications

  • 100/200 Gbps OTN Muxponders and 2.5Gbps – 100Gbps GPON Platform.
  • Solid State Radar Platforms.
  • Low Latency Ethernet Network Interfaces.
  • High-Bandwidth PCIe interfaces.
  • HD video and vision processing.

Specifications

Identity

Part Number
GTS PMA/FEC Direct PHY IP
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
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Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Frequently asked questions about Multi-Protocol PHY IP cores

What is GTS PMA/FEC Direct PHY IP?

GTS PMA/FEC Direct PHY IP is a Multi-Protocol PHY IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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