Vendor: Altera Category: MIPI PHY

MIPI D-PHY IP

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and receptio…

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Overview

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.

*Only in Agilex™ 5 FPGA E-Series Group A and D-Series devices.

Key features

  • MIPI D-PHY
    • MIPI D-PHY feature supports high-speed (HS) and low-power (LP) modes and allows direct interface with the D-PHY compliance component without external components.
    • Supports low-power and high-speed signaling up to 3.5 Gbps* per lane.
    • Supports AXI-Lite interface for seamless video transmission and reception.
    • Enables unidirectional multi-lane configurations 1, 2, 4, or 8 lanes.
  • MIPI CSI-2
    • Latency Reduction and Transport Efficiency (LRTE) for image-sensor aggregation without adding to the overall system cost.
    • Differential Pulse Code Modulation (DPCM) compression for seamless compression of HD images for mission critical applications.
    • Reducing the number of wires in a system like IoT by using the Unified Serial Link (USL).
    • Scrambling reduces Power Spectral Density (PSD) emissions for longer channels.
  • MIPI DSI-2
    • High Resolution Support: MIPI DSI-2 supports high-resolution displays, including 4K, 5K UHD+, and 8K UHD resolutions
    • VESA Display Compression-M (VDC-M) Compliance: It is compliant with VESA VDC-M 1.2, supporting various encoding mechanisms like BP, transform, MPP, MPP fallback, and BP skip
    • Flexible Video Input Formats: Supports 8, 10, or 12 bits per component video, with 4:4:4 sampling for RGB and 4:4:4, 4:2:2, and 4:2:0 sampling for YCbCr video input formats
    • High Pixel Throughput: Capable of processing two pixels per clock per hard slice encoder, with parameterizable parallel slice encoder instances to adapt to different display resolutions

Block Diagram

MIPI D-PHY IP block diagram

Applications

  • 4K and 8K Image and Video Streaming.
  • Automotive – ADAS, In-Vehicle Infotainment, Electrification & Networking.
  • Sensor imaging and connectivity on UAV and Robotic Platforms.
  • Virtual Reality Headsets, Camera-enabled robots and drones.

Specifications

Identity

Part Number
MIPI D-PHY IP
Vendor
Altera
Type
Silicon IP

Standards & Interfaces

MIPI PHY
MIPI D-PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about MIPI PHY IP core

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Frequently asked questions about MIPI PHY IP

What is MIPI D-PHY IP?

MIPI D-PHY IP is a MIPI PHY IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this MIPI PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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