Vendor: Arasan Chip Systems Inc. Category: Single-Protocol PHY

I3C PHY

The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself …

Contact Provider Request Datasheet

Overview

The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself and various sensor devices. The I3C interface is intended to improve upon the features of the I2C interface, preserving backward compatibility. This I3C defines a standard multi-Drop interface between Host processors and peripheral Devices (e.g., sensors). Implementing the I3C Specification greatly increases the flexibility system designers have to supplant incumbent interfaces (i.e., I2C, SPI, UART) and support a wide array of Devices of increasing complexity and diversity in their system (e.g., sensor subsystem) and at as low a cost as possible.

The I3C PHY is functionality of the MIPI I3C v1.2. It has two primary blocks, the Digital Front End (DFE) and Analog Front End (AFE).

Key features

  • Compliant with MIPI I3C specification Version 1.2
  • Support data transfer up to 12.5 MHz operation during Push-Pull
  • Support open drain mode
  • Support Single Data Rate messaging (SDR)
  • Support High Data Rate Messaging Modes
  • HDR-DDR for Double Data Rate
  • HDR-TSL for Ternary Symbol Legacy-Inclusive-Bus
  • HDR-TSP for Ternary Symbol for Pure Bus
  • Support legacy I2C devices
  • Support Dynamic Addressing while supporting Static Addressing for Legacy I2C devices
  • Support Reception of In-band Interrupt support from the I3C Slave devices
  • Support Reception of Hot-Join from newly added I3C Slave devices
  • Support Target reset
  • Support Group Addressing
  • Support Synchronous Timing Support and Asynchronous Time Stamping

Block Diagram

I3C PHY block diagram

What’s Included?

  • GDS-II
  • CDL netlist for LVS
  • LVS reports
  • DRC and Antenna reports
  • LIB files
  • User guide and Integration Guides
  • LEF
  • Behavioral models
  • IBIS Models

Specifications

Identity

Part Number
I3C PHY
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Arasan Chip Systems Inc.

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Arasan’s xSPI/eMMC5.1 PHY: Unified Dual-Mode Physical Layer IP

As SoCs evolve to support a growing range of memory interfaces, designers are faced with the challenge of balancing integration complexity, pin efficiency, and performance scalability. Traditionally, implementing both xSPI (JESD251) for boot and eMMC 5.1 for high-speed storage required separate PHYs, leading to increased silicon area, power consumption, and I/O overhead.

Frequently asked questions about Single-Protocol PHY IP

What is I3C PHY?

I3C PHY is a Single-Protocol PHY IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP