What is Mini-LVDS TX and RX PHY?
Mini-LVDS TX and RX PHY is a Single-Protocol PHY IP core from VEGA Semiconductor listed on Semi IP Hub. It is listed with support for tsmc Available on request.
Vendor:
VEGA Semiconductor
Category:
Single-Protocol PHY
Mini-LVDS TX and RX PHY
The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process.
Overview
The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process. It is suitable for the interface between the timing controller and column drivers.
Key features
- Process: TSMC 180nm 1.8V/5V 1P6M BCD process
- Area: 1750um x 850um
- RX
- Total 4 RX data lanes and two RX clock lanes
- Input data rate: 56Mbps ~ 336Mbps
- 1:56 serial to parallel ratio
- Input voltage range: 0V to 1.4V
- Input differential threshold: +/- 100mV
- One lane current consumption: AVDD_RX: 0.6mA, AVDD18:1.4mA
- One lane leakage< 1uA
- TX
- Total 4 TX data lanes and two TX clock lanes
- Output data rate: 56Mbps ~ 336Mbps
- 56:1 parallel to serial ratio
- Output common mode voltage: 0.6V to 1.4V
- Adjustable Tx Clock output driving(x1,x2,x3,x5): 1.75mA/3.5 mA/5.25 mA/8.75 mA
- Tri-state and power off for individual Tx Data/Clock output
- One lane current consumption: AVDD_TX(x1): 2.6mA, AVDD18:0.2mA
- One lane leakage< 5uA
- Operated Ambient Temperature: Ta = -40 ~ 85°C
- Operated Junction Temperature: Tj = -40~125°C
Block Diagram
T180BCDLVDSV1 block diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Available on request |
Specifications
Identity
Part Number
T180BCDLVDSV1
Vendor
VEGA Semiconductor
Type
Silicon IP
Provider
HQ:
Taiwan
Frequently asked questions about Single-Protocol PHY IP
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.