Vendor: Algo-Logic Systems Category: Single-Protocol PHY

Ultra-Low-Latency 10GE PHY+MAC

Having the lowest network latency is critical for Accelerated Finance.

Overview

Having the lowest network latency is critical for Accelerated Finance. To achieve the lowest Ethernet latency, it is necessary to optimize the layer-1 PHY and the layer-2 MAC. The Ultra-Low-Latency (ULL) PHY+MAC minimizes roundtrip latency by several hundred nanoseconds as compared to vendor supplied IP cores. The  ULL PHY+MAC design implements 10GBASE-R MAC and PCS (Physical Coding Sub-layer) functionality in an FPGA by using logic optimized for latency.

The ULL PHY+MAC is compatible with multiple FPGA platforms that support SERDES rates of 10.3125 Gbps while bypassing all PCS and excessive buffering features. The MAC interfaces to user logic via the 64-bit Avalon-ST bus or AXI4-Stream standards.

In this fashion, the ULL PHY+MAC is designed to seamlessly replace much slower default PHY+MAC implementations that come with standard FPGA platforms.

Key features

  • Ultra-low-latency round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit 
  • Reconciliation sub-layer implementation compliant with IEEE802.3 
  • Local fault and remote fault detection and handling 
  • Frame Check Sequence (FCS) insertion and verification at line rate 
  • Automatic transmit padding, jumbo frame support, transmit and receive statistics counters 
  • Compatible with multiple FPGA platforms as soft-logic around SERDES 
  • Supports both standard Avalon-ST / AXI4-Stream bus interfaces  
  • Direct replacement for high-latency default vendor cores 
  • High level architecture Ethernet MAC design is flexible in its use of system clock (on the  Avalon ST side) 
  • Low gate count  

Block Diagram

AL-10G-PHYMAC block diagram

Applications

  • High Frequency Trading (HFT) 
    • Market makers, trading firms, stock exchanges  
  • High-performance datacenter networks 
    • Enables world's fastest key/value search over Ethernet 
  • Real-time Internet data collection  

Specifications

Identity

Part Number
AL-10G-PHYMAC
Vendor
Algo-Logic Systems
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Single-Protocol PHY IP

What is Ultra-Low-Latency 10GE PHY+MAC?

Ultra-Low-Latency 10GE PHY+MAC is a Single-Protocol PHY IP core from Algo-Logic Systems listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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