Vendor: Faststream Technologies Category: Single-Protocol PHY

LVDS transceiver IP

The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream.

Overview

The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream. This serial stream clarifies the move of 12-bit or less bus over PCB finds and cables by removing the skew problems between parallel data and clock paths.Each transmitter takes a single-ended input, and generates an LVDS differential output. The receiver, on the other hand, accepts an LVDS input signal at low voltage levels and converts it into a single-ended signal.In addition, this SERDES pair has built-in system and device test capability.
The line loopback characteristics allows a user to check the probity of the serial data transmission path of the transmitter and receiver while deserializing the serial data to parallel data at the receiver output.

Key features

  • Low power dissipation
  • Integrated termination resistors in transmitter and receiver.
  • Level Shifting and single-ended to differential conversion included
  • Wide reference clock frequency tolerance: +/-500ppm
  • Internal PLL, no external PLL components are required
  • >2.0kV HBM ESD
  • Full industrial operating temperature range: -40 ~ +125 °C
  • Programmable pre-emphasis (0dB / 3dB / 6dB / 9dB)
  • Compatible with the TIA/EIA-644-A LVDS standard
  • Modular design to facilitate customization and process migration
  • Can be easily integrated into multiple Channels

What’s Included?

  • Data Sheet
  • GDSII
  • LVS Netlist
  • Integration Guidelines
  • Timing Model
  • Behavioral Model
  • LEF File for P&R

Specifications

Identity

Part Number
FST-LVDS-TxRx
Vendor
Faststream Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is LVDS transceiver IP?

LVDS transceiver IP is a Single-Protocol PHY IP core from Faststream Technologies listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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