Vendor: T2M GmbH Category: Single-Protocol PHY

LVDS Rx IP, Silicon Proven in GF 28LPe

A physical layer IP for LVDS Receiver.

Overview

A physical layer IP for LVDS Receiver. This IP consists of 20-lane (4 x 4D1C) LVDS receivers and supports up to 1.5Gbps data rate. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

Key features

  • LVDS compliant Rx
  • 4 groups of 4-Data, 1-Clock channels
  • Each lane/group can be turned on/off individually
  • Supports from 168Mbps to 1.5Gbps data rate
  • Configurable analog characteristics
  • Bias voltage/current
  • DLL characteristics
  • Testability Internal analog nodes can be observed through a test pad DLL test mode Process
  • Supply Voltage 1.8V/0.9V
  • Silicon Proven in SMIC 14nm SF+

Block Diagram

LVDS Rx IP in 28SLP block diagram

What’s Included?

  • Datasheet
  • Integration guideline
  • GDSII or Phantom
  • GDSII Layer map table
  • CDL netlist for LVS
  • LEF Verilog behaviour model
  • Liberty timing model DRC/LVS/ERC results

Specifications

Identity

Part Number
LVDS Rx IP in 28SLP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is LVDS Rx IP, Silicon Proven in GF 28LPe?

LVDS Rx IP, Silicon Proven in GF 28LPe is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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