PCIe 4.0 PHY, SS 14LPU x4, North/South (vertical) poly orientation for Automotive AEC-Q100 Grade 1
The multi-channel PHY IP for PCI Express® 4.0 includes the high-speed, high-performance transceiver to meet today’s applications’…
- PCIe Gen4
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
PCIe 4.0 PHY, SS 14LPU x4, North/South (vertical) poly orientation for Automotive AEC-Q100 Grade 1
The multi-channel PHY IP for PCI Express® 4.0 includes the high-speed, high-performance transceiver to meet today’s applications’…
PCIe 4.0 PHY, SS 14LPU x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® 4.0 includes the high-speed, high-performance transceiver to meet today’s applications’…
PCIe 4.0 PHY, SS 14LPP x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® 4.0 includes the high-speed, high-performance transceiver to meet today’s applications’…
PCIe 4.0 PHY, SS 11LPP x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® 4.0 includes the high-speed, high-performance transceiver to meet today’s applications’…
PCIe 4.0 PHY, SS 11LPP x2, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® 4.0 includes the high-speed, high-performance transceiver to meet today’s applications’…
PCIe 4.0 PHY, SS 11LPP x1, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® 4.0 includes the high-speed, high-performance transceiver to meet today’s applications’…
Multi-Port Switch IP for PCI Express
The IP for PCI Express with Single Root I/O Virtualization (SR-IOV) implements a configurable and scalable SR-IOV solution provid…
IDE Security IP Modules for PCI Express 7.0
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices, to…
PCIe 7.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across back…
The USB 3.2 SuperSpeed Plus PHY provides a range of USB 3.2 Gen2 host and peripheral applications at up to 10 Gbps per lane, whic…
The USB 2.0 PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
Physical Layer Interface for SD and eMMC Storage Devices
Physical Layer of LVDS Receiver
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
This 1-lane to 4-lane PCIE PHY includes all high-speed analog functions for high-speed data transport between chips over PCBs and…
The Enterprise Ethernet PCS Controller IP (XLGPCS) provides an interface between a Media Access Controller (MAC) and Physical Med…
Automotive (AP) version of the DWC Enterprise PCS.
The Enterprise Ethernet PCS Controller IP (XLGPCS) provides an interface between a Media Access Controller (MAC) and Physical Med…
25G Automotive (AC) version of the Enterprise / XLG PCS
The Enterprise Ethernet PCS Controller IP (XLGPCS) provides an interface between a Media Access Controller (MAC) and Physical Med…
High Speed Ethernet Quad 10G to 100G PCS
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet Gen-2 Quad 100G PCS IP
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…