Vendor: T2M GmbH Category: Single-Protocol PHY

USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)

A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data c…

Overview

A high performance, high-speed SERDES IP called USB3.1Type-C PHY is created for semiconductors that provide high bandwidth data connection while using less power. A specific design for USB 3.1 type-C applications is the USB 3.1Type-C PHY IP. A dedicated PCS can be provided together with the USB 3.1 Type C PHY IP to complete functionality of various applications, including elastic buffer, scramble/de-scramble, data encoding/decoding, PRBS generation/checking, registers control and testing. Depending on the customer's choice, PCS is offered as either a hard or soft macro; additionally, the PCS specification will be made available separately. Using a test bench constructed in Verilog HDL, the NC-Verilog simulation software verifies PHY functionality.

Key features

  • Support half rate mode (5Gbps) and full rate mode (10Gbps)
  • Tolerate max +/-7000ppm input frequency offset
  • 32bit/40bit selectable parallel data bus
  • Programmable transmit amplitude
  • 3 taps/2 taps selectable FFE
  • Receiver CTLE and One-tap perspective DFE
  • Build in self-test with PRBS7/31 pattern generation and checker for production test
  • Integrated on-die termination resistors
  • Support receiver detection
  • Support LFPS signal generation and detection
  • Support Spread Spectrum clock generation and receiving
  • Flexible reference clock frequency
  • Do not need any external component
  • ESD: HBM/MM/CDM/Latch Up2000V/200V/500V/100mA
  • Metal Layer:M1~M7+RDL
  • Core Voltage: 1.1V
  • IO Voltage: 3.3V
  • Silicon Proven in UMC 55SP/EF.

Block Diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behavior model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Specifications

Identity

Part Number
USB 3.1 Type-C PHY IP in 55SP/EF
Vendor
T2M GmbH
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 3.1

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

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Frequently asked questions about Single-Protocol PHY IP

What is USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF)?

USB-C 3.1 SS/SSP PHY, Type-C IP (Silicon proven in UMC 55SP/ EF) is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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