A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued repre…
- Control Logic
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
A numerically controlled oscillator (NCO) is a digital signal generator, which synthesizes a discrete-time, discrete-valued repre…
High-Speed Reed Solomon Intel® FPGA IP Core
The High-Speed Reed Solomon Intel® FPGA intellectual property (IP) core uses a large parallel architecture to achieve a large thr…
The FIR II Intel IP core provides a fully-integrated finite impulse response (FIR) filter function optimized for use with Intel F…
The Fast Fourier transform (FFT) Intel FPGA intellectual property (IP) core is a high-performance, parameterizable FFT processor.
The CIC Intel FPGA IP core implements a Cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon…
The Bose, Chaudhuri, and Hocquenghem (BCH) error correction intellectual property (IP) core is typically used in NAND flash appli…
The 5G Polar Intel® FPGA IP implements a forward error correction (FEC) encoder and decoder based on polar codes compliant with t…
Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy…
OFDM - Orthogonal Frequency Division Multiplexing
OFDM - Orthogonal Frequency Division Multiplexing
MIPI I3C Master RISC-V based subsystem
RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products …
100G UDP Offload Engine - Offloads UDP packet processing for efficient, high-speed networking
The 100G UDP Offload Engine in Verification IP (VIP) offloads UDP packet processing to specialized hardware, enhancing data trans…
100G TCP/IP Offload Engine - Validates high-speed network traffic, optimizing flow and reliability
The 100G TCP/IP Offload Engine is a cutting-edge Verification IP designed to streamline the testing of high-speed networking inte…
ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
The AndesCore™ D23-SE is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with …
Falcon IP Core is a post-quantum digital signature algorithm (DSA).
Error Correcting Code for SRAMs
The ECC-SRAM core adds protection against SRAM data corruption.
Highly customizable processor IP supporting the Lua scripting language
A highly customizable processor IP, that supports the Lua scripting language.
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…