The D68HC11F is a synthesisable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard.
- MCU
- now
- D68HC11F1
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
The D68HC11F is a synthesisable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard.
8-bit Microcontroller IP - legacy architecture - raplacement of 68HC11K MCU's
The D68HC11K is synthesisable soft IP Core Microcontroller, fully compatible with the Motorola MC68HC11K industry standard.
The D6803 is synthesisable, SOFT Microcontroller IP Core, fully compatible with the Motorola MC6803.
The eSi-QRD-LSL is a QR-Decomposition Least Squares Lattice (QRD-LSL) core is a high throughput IP core that finds application in…
A efficient pipelined radix-2 squared FFT.
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream.
16/32-bit Microprocessor with BDM
The D68000-BDM soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor.
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encodi…
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer.
Maximum normalised correlation core
The eSi-MNC core provides the control and data plane interfaces to a Maximum Normalised Correlation module.
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator.
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements.
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
High-performance implementation of Z80/Z180 instruction set
Two clock cycle machine cycle implementation of the Z80/Z180 instruction set.
The D6802 is a 8-bit MPU IP Core.
The MVD DVB-S core is a drop-in module that includes the following functions: - Input data framer from DVB-SPI source (MPEG-TS fl…