Multi-channel DVB-C / J83 FEC encoder

The CMS0044 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified by DVB-C and by J83 Annexes A B and C. It is designed to interface to external modulators or advanced upconverting DACs such as the Analog Devices AD9789.

The CMS0044 includes functions for framing, scrambling, interleaving, Reed-Solomon coding, trellis coding, and QAM mapping.

The requirements of J83A J83C and DVB-C are virtually identical, but are quite different to the requirements for J83B. With the exception of the common interleaver block, two independent datapaths are required, as shown above.

The multi-channel encoder uses a common transmission mode, so symbol timing is common for all channels. The encoder may be built with individual interleave modes, as this does not impact data symbol timing. However, this requires more memory bandwidth.

• Provides a multi-channel FEC encoding solution for cable transmission compliant with DVB-C (EN 300 429); ITU J.83ABC; DOCSIS 1.0-3.0 and SCTE 07.
• Scalable architecture supports 1 to 4 channels per core, and multiple instances per FPGA.
• Mapped and unmapped symbol data outputs
• Supports AD9789 Signal-Processing DAC.
• 4-channel cores may be cascaded, allowing multiple cores to arbitrate into a single external SRAM.
• Extension core available for SPI/ASI interface with integrated PCR TS re-stamping, NULL TS packet removal/filtering and NULL/PRBS TS packet insertion. TS interface accepts 188- or 204-byte MPEG packets
• Seamless integration with Altera ASI megacore when using SPI/ASI extension core.
• Optional input and output TS rate estimation registers.
• Synthesis control to build for any subset of the supported modes, minimizing logic.
• Designed for very efficient FPGA implementation without compromise to the targeting of gate array or standard cell structures such as Altera HardCopy.
• C / C++ header file defines Host Interface registers, facilitating software mode control.