What is MIPI I3C Master RISC-V based subsystem?
MIPI I3C Master RISC-V based subsystem is a CPU IP core from MAXVY Technologies Pvt Ltd listed on Semi IP Hub.
Vendor:
MAXVY Technologies Pvt Ltd
Category:
CPU
MIPI I3C Master RISC-V based subsystem
RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products …
Overview
RISC-V based MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interface for sensors. All the basic functionalities of MIPI I3C master has been proved with Microsemi smart fusion 2 creative development board .In addition the MIPI I3C master supports for both AHB lite and APB Interface.
Key features
- Dynamic address assignment.
- Host controller compliance
- SDA arbitration.
- Data transfer with and without broadcast.
- All basic CCC command features.
- Both push-pull and open drain mode transaction.
- Private write and read operations.
Block Diagram
MIPI I3C Host RISC-V based subsystem block diagram
Specifications
Identity
Part Number
MIPI I3C Host RISC-V based subsystem
Vendor
MAXVY Technologies Pvt Ltd
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
Frequently asked questions about CPU IP cores
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