Vendor: Semidynamics Category: NPU

All-In-One RISC-V NPU

Unified Architecture for Cutting-Edge Intelligence

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Overview

Unified Architecture for Cutting-Edge Intelligence

Customizable Throughput  
Offers modular scaling to meet extreme processing demands, from localized devices to massive infrastructure

Seamless Hardware Fusion 
Integrates multiple compute engines into one system to remove bottlenecks and ensure instantaneous execution

Open-Source Flexibility 
Provides a fully programmable environment that eliminates proprietary restrictions for modern language models and deep learning

Standard Data Type Support

  • Activations: INT8, INT16, INT32, INT64, FP16, FP32, FP64 (*)
  • Convolutions: INT4, INT8, INT16, FP16, BF16 (*)

(*) Configuration options available

Architecture Highlights

  • Scalable NPU Core for AI
  • Configurable from 8-64 TOPS
  • RISC-V Based All-In-One architecture (CPU, Vector, and Tensor)

Block Diagram

Cervell™ block diagram

Benefits

All-in-One Processing

  • CPU, Vector, and Tensor seamlessly combined for zero-latency AI workload

Standard RISC-V AI Acceleration

  • Fully programmable, no vendor lock-in

Ideal for

  • LLMs, Deep Learning, Edge AI, AI Datacenters

High Efficiency

  • AI acceleration optimized for LLMs, Recommendation Systems, and Deep Learning

Specifications

Identity

Part Number
Cervell™
Vendor
Semidynamics
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Variants in this family

Part Number Short Description
Cervell™ NPU C1 NPU IP Core for Edge AI
Cervell™ NPU C8 Higher‑Throughput NPU IP Core
Cervell™ NPU C32 Clustered IP to Scale Throughput

Provider

Semidynamics
HQ: Spain
Contact Semidynamics

Learn more about NPU IP core

Benchmarking an NPU at Scale

With every SDK release, Quadric automatically recompiles and re-profiles the entire model zoo across a broad sweep of hardware configurations. The results land in DevStudio for any SoC architect to explore — no sales call, no handpicked numbers.

Your NPU Learned to Listen

Whisper runs end-to-end on Chimera. Encoder and decoder compiled as native GPNPU kernels, INT4 weights, FP16 attention, top-1 token match against the float32 reference. Scales to four cores with a flag, no recompile.

Heterogeneous NPU Data Movement Tax: Intel's Own Slides Tell the Story

At Quadric, we have long argued that heterogeneous NPU designs — those that stitch together multiple specialized fixed-function engines — carry an unavoidable hidden cost: data has to move. A lot. And data movement burns power, adds latency, and creates silicon-area overhead that scales with every new generation of AI models. Now, Intel has made that case for us.

Frequently asked questions about NPU IP cores

What is All-In-One RISC-V NPU?

All-In-One RISC-V NPU is a NPU IP core from Semidynamics listed on Semi IP Hub.

How should engineers evaluate this NPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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