CRC (Cyclic Redundancy Check) Calculation Unit
CRC (Cyclic Redundancy Check) calculation unit using a polynomial generator from 8-bit/16-bit/32-bit data words CRC code.
- Control Logic
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
CRC (Cyclic Redundancy Check) Calculation Unit
CRC (Cyclic Redundancy Check) calculation unit using a polynomial generator from 8-bit/16-bit/32-bit data words CRC code.
The Neural-Network Accelerators (NACC) improves the inference performance of neural networks.
Safety Enhanced GPNPU Processor IP
Automotive applications are uniquely demanding for any AI acceleration solution.
ARC Functional Safety Software
Today’s complex automotive applications require robust safety related hardware and software to meet the increasingly stringent au…
AI DSA Processor - 9-Stage Pipeline, Dual-issue
NI900 is a DSA processor based on 900 Series.
ARC-V RPX Series Functional Safety Processor IP
The ARC-V™ RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-…
Double & Single Precision IEEE-754 complete FPU
The A2FD is a fully synthesizable module implemented in Verilog RTL.
Very high performance IEEE-754 modules
The A2FM product is a collection of floating-point execution units compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for B…
Traditional processors no longer strike the right balance between high performance, energy consumption, and cost.
Flow's Parallel Processing Unit solves one of computing's most fundamental dilemmas - parallel processing.
Unified Architecture for Cutting-Edge Intelligence
Multi-channel DVB-C / J83 FEC encoder
The CMS0044 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified b…
The CMS0045 ISDB-T Modulator provides all the necessary processing steps to modulate one, two or three transport stream into a co…
The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X wide-band dig…
Configurable RISC-V processor IP core
The NOEL3 is a configurable RISC-V processor IP core, described in VHDL.
Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source …
The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implem…
Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems.
Reed Solomon II Intel® FPGA IP Core
The Reed Solomon II Intel® FPGA intellectual property (IP) core offers a fully parameterizable Reed Solomon encoder and decoder.
The Reed-Solomon (RS) compiler offers a fully parameterizable RS coder and RS decoder.