High Throughput and Low Latency Data Compression Engine
This IP implements a proprietary modified LZ77 algorithm and provides very high speed data compression with low latency and very …
- Data Compression
- Proven in Product
- now
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
High Throughput and Low Latency Data Compression Engine
This IP implements a proprietary modified LZ77 algorithm and provides very high speed data compression with low latency and very …
The K-best decoder is part of the MIMO decoder.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
The LTE Lite PHY supplied as a portable and synthesizable Verilog-2001 IP.
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps …
The K-best decoder is part of the MIMO decoder.
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block).
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications.
TC5100 is a flexible LDPC encoder/decoder Core.
Lossless / Near lossless Encoder / Decoder Hardware IP
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SPC (Synthesizable Programmable Core) is a soft FPGA core that is fully integrated into standard design flows and that allows the…
The MVD ISDB-T core is a drop-in module that includes the following functions : • Input data framer from DVB-SPI source (MPEG-TS …
Reconfigurable Parallel CRC Generator
Parallel CRC IP is reconfigurable high-speed CRC generator, flexible in terms of input data width and generating polynomial.
Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)
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8-Channel PCM-to-PWM Modulator in Fujitsu 55nm
The AR35F01A is a digitally coded conversion IP that translates 8-ch (4 stereo channels) of 16-24bit pulse-code modulated (PCM) i…
High Throughput and Low Latency Compression Engine For SSD
The high performance compression IPhere compresses at the line rate of 16Gbps in ASIC or up to 64 Gbps for custom implementations.