16-ACS Multi Function Viterbi Decoder
The VA08VB is a medium complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
- Channel Coding
- Now
- 3GPP TS 25.212 V5.2.0 Relea…
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
16-ACS Multi Function Viterbi Decoder
The VA08VB is a medium complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
For device makers, a small, inexpensive, low-power chip that can run the large AI models is needed to lead the market with their …
Efficiently supports front-end audio processing like beamforming and noise reduction, as well as neural network-assisted speech r…
100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input
The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm wit…
CCSDS 231.0 LDPC(128, 64) and LDPC(512, 256) Encoder and Decoder
The IPrium-LDPC-CCSDS-231-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm f…
Even the smallest, lowest-power audio devices embed AI capabilities to enhance the user experience.
The MIMO Decoder accepts two independent input streams, and the channel estimation matrix.
CCSDS AR4JA LDPC Decoder & Encoder
The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding diff…
CCSDS AR4JA LDPC Encoder/Decoder
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, …
LDPC corrects errors caused by flash storage failure mechanisms.
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
Designed to enable low power signal conditioning for IoT edge endpoints.
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000’s CPU32 version of the 32-bit microcontroller.
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizab…
Highest performance real-time processor
Highest-performance Cortex-R processor with memory management unit (MMU), enabling real-time and rich operating systems (OS), suc…
Kalman Filter hardware accelerator
The eSi-Kalman core provides hardware acceleration for Kalman Filtering (KF) and related target tracking algorithms, such as meas…
High performance FFT optimised for Radar
A configurable efficient pipelined radix-2 squared FFT with additional functionality making it optimised for point cloud generati…
The IntelliProp IPC-BL119A-ZM is a configurable IP core that provides a method of extending an information block with extra bits …
Ceva-MotionEngine is Ceva’s core sensor processing software system and is the product of over 20 years of experience developing s…